Analogue/Digital Conversion Calibration/Testing TRIZ Cases
- A/D Converter Input Checking Circuit Using Dual Derived Signals
Dual derived analog signals are compared within a tolerance range to detect faults and EMI in A/D converter input circuits.
- RF DAC Background Error Measurement Using Transparent Dither
Transparent dither and cross-correlation extract static and timing skew errors in RF DAC cells, improving linearity with low calibration overhead.
- ADC Input Switching for Signal Line Disconnection Detection
By switching to a reference voltage before sampling an input, this ADC detects line disconnection without pull-down resistors and extra circuit scale.
- ADC Nonlinearity Testing Using Counter-Based Code Histograms
Counter-based code histograms characterize ADC DNL and INL with lower noise sensitivity, less data storage, and simpler high-speed testing.
- Switched-Capacitor ADC Calibration Using a Supplementary DAC
A built-in supplementary DAC shifts the ADC transfer curve to measure offset and gain error quickly without high-accuracy test equipment.
- On-Chip Pattern Generator for Full-Speed DAC Characterization
An on-chip pattern generator bypasses IC I/O speed limits, enabling full-rate DAC testing through a low-speed interface without extra pins.
- ADC Linearity Calibration Using Dual Acquisition Times
Dual acquisition times let an ADC self-calibrate linearity, cutting calibration equipment complexity while preserving high conversion accuracy.
- Track-and-Hold Dither Injection for Interleaved ADC Mismatch
Additive and multiplicative dither in a shared track-and-hold calibrates interleaved ADC nonlinearity, gain, offset, and mismatch.
- TDC Calibration Circuit With Dynamic Delay Resolution Control
A calibrated multi-bit delay chain adjusts TDC resolution to track one DCO period, improving timing accuracy across PVT and frequency changes.
- SAR ADC Capacitive DAC Calibration for Mismatch Linearity
Calibrating each SAR ADC DAC capacitor from LSB upward corrects mismatch, preserves parasitics, and enables faster settling with better linearity.
- Asynchronous SAR ADC Delay Tuning for DAC Settling Accuracy
Testing and calibrating comparator delay lets asynchronous SAR ADCs preserve DAC settling accuracy without unnecessarily extending conversion time.
- Multi-Stage ADC Calibration for Interleaving Error Correction
Digital calibration corrects clock skew, gain, and offset errors in multi-stage ADCs to preserve high sample rates with better accuracy.
- Current-Controlled MDAC for Time-Interleaved ADC Accuracy
A current-controlled MDAC with phased current generation and calibration helps time-interleaved ADCs limit skew, gain, and offset errors.
- SAR ADC Capacitive DAC Calibration for Mismatch and Settling Speed
LSB-first capacitive DAC calibration corrects SAR ADC capacitor mismatch, preserving linearity while allowing smaller capacitors and faster settling.
- Successive Approximation ADC Calibration Without Separate Multipliers
Folding multiplication and offset addition into ADC control cuts die area and processing time while preserving calibration accuracy.
- Time-Interleaved ADC Output Downsampling for Easier Testing
Downsampling interleaved ADC channel outputs lowers digital signal frequency, cutting pin count and test instrument demands.
- DAC Boundary Signal Measurement for Timing and Amplitude Errors
Routes DAC boundary-transition signal portions into a measurement path to detect timing and amplitude errors without disrupting conversion.
- Time-Interleaved ADC Calibration for Channel Mismatch Images
A filter and calculating circuit reconstruct and cancel mismatch-induced interference images in time-interleaved ADCs to reduce distortion.
- Mixed-Signal DAC Switching Calibration for Low Third-Order Distortion
Calibrating mixed-signal DAC switching with measured node voltages cuts third-order distortion and timing mismatch at high conversion speeds.
- SAR ADC Self-Test Circuit for Internal Failure Diagnosis
Internal SAR ADC self-test reuses the DAC and comparator to detect failures and locate performance degradation without external test circuits.
- Capacitor-Array ADC Dithering for Lower DNL and No Missing Codes
A capacitor-array dither scheme uses a second capacitor group and sequence control to reduce DNL errors and eliminate missing codes.
- ADC Calibration Iterative Loop for Switch-Mode Power Supplies
An iterative loop process replaces complex quadratic calculations to reduce processing time and memory usage during ADC calibration.
- Time-Interleaved ADC Timing Calibration via Correlation Feedback
A timing calibrator computes calibration values from correlation data between adjacent converter samples to adjust clock phases.