On-Chip Pattern Generator for Full-Speed DAC Characterization
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Solution Overview
Problem
High-speed digital-to-analog converter (DAC) measurement setups are limited by the Integrated Circuit (IC) I/O interface, which restricts testing to less than the full conversion rate, even with advanced arbitrary waveform generators, due to the bottleneck at the IC interface.
Innovation Solution
Incorporating an on-chip pattern generator with a series of D flip-flops, which allows data input through a low-speed interface like SPI or I2C, enabling data delivery at the DAC's maximum data rate without relying on the IC I/O interface, thus bypassing the speed limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional external AWG and IC interface are used for DAC testing, then device complexity is reduced, but data rate is limited to below full conversion rate due to IC I/O bottleneck
Solution Approach 1:
The patent merges the pattern generator functionality directly into the DAC chip by integrating a series of D flip-flops on the same semiconductor substrate. This integration eliminates the external AWG and IC I/O interface bottleneck, enabling data input at the full conversion rate of the DAC without being limited by external interface speeds.
Solution Approach 2:
The pattern generator is nested within the DAC structure, with D flip-flops embedded inside the DAC chip. The input multiplexer is also integrated within the same chip, creating a hierarchical structure where the pattern generator is contained within the DAC device itself, allowing high-speed operation without external interface limitations.
2Speed
If on-chip pattern generator with D flip-flops is integrated into DAC, then data rate reaches full conversion rate, but device complexity increases
Solution Approach 1:
The pattern generator and DAC share the same semiconductor substrate and clock signal, merging their operations. The D flip-flops are directly connected to the DAC input, eliminating the need for external high-speed interfaces and enabling the DAC to operate at its full conversion rate capability.
Solution Approach 2:
The DAC chip generates its own test patterns using the integrated D flip-flops, eliminating the need for external pattern generation equipment. The system is self-sufficient for testing and characterization at full speed, requiring only a clock source and control signals through existing low-speed interfaces.
3Speed
If external AWG is used for high-speed data input, then data rate can be multi-giga Hertz, but IC I/O interface limits it to one-giga Hertz
Solution Approach 1:
The patent extracts the pattern generation functionality from the external test equipment and relocates it directly onto the DAC chip. This extraction removes the IC I/O interface bottleneck that limited the data rate to one-giga Hertz, allowing the DAC to receive test data at its full multi-giga Hertz conversion rate capability.
4Productivity
If on-chip pattern generator is added to DAC, then extra pins and design complexity increase, but the solution requires no extra pins
Solution Approach 1:
The integrated D flip-flops and input multiplexer serve multiple functions: they act as both the pattern generator for testing and as part of the normal data input path for the DAC. The existing IC interface pins are reused for controlling the multiplexer and loading patterns, eliminating the need for additional dedicated pins for the pattern generator function.
Data Source
AI summary
A method of enabling full speed test and characterization for high-speed Digital-to-Analog Converter (DAC) by employing an on-chip pattern generator. The test pattern is written to the on-chip pattern generator through a low data rate Integrated circuit (IC) interface, and the pattern generator is then enabled and coupled to DAC to facilitate full speed test for DAC. This method does not require extra input/output pin or extra process and minimize design complexity.