SAR ADC Capacitive DAC Calibration for Mismatch and Settling Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Capacitive DACs in SAR ADCs face linearity issues due to capacitor mismatch, which worsens with smaller capacitor values, affecting the converter's performance and linearity.
Innovation Solution
A capacitive DAC calibration process is introduced, using a calibration capacitor to correct capacitor mismatch by incrementally adjusting the value of each capacitor until the ideal value is found, leveraging binary weighted capacitor characteristics without altering the normal binary search configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller capacitor values are used for faster DAC settling, then settling time is reduced, but capacitor mismatch worsens
Solution Approach 1:
The patent applies preliminary action by performing capacitor calibration before the actual ADC conversion process. The calibration process pre-adjusts the capacitor values to compensate for manufacturing mismatches, ensuring that when the DAC operates with smaller capacitor values for faster settling, the pre-corrected values maintain linearity accuracy.
Solution Approach 2:
The patent changes the capacitor values dynamically during calibration by adjusting the number of parallel unit capacitors activated for each capacitor element. This parameter adjustment allows the system to optimize the balance between settling time and mismatch, selecting the minimal capacitor value that still achieves acceptable linearity after calibration correction.
2Manufacturing precision
If capacitor calibration is performed to correct mismatch, then linearity is improved, but device complexity increases
Solution Approach 1:
The patent segments the calibration process into individual capacitor elements, calibrating each capacitor separately by adjusting its parallel unit capacitor count. This segmentation allows the complex calibration task to be broken down into manageable steps, where each capacitor is calibrated independently using a systematic approach that reduces overall complexity.
Solution Approach 2:
The calibration process uses the existing DAC and comparator circuitry to perform self-calibration without requiring external calibration equipment. The system uses its own components (DAC, comparator, and control logic) to measure and adjust capacitor values, making the calibration process self-contained and reducing external complexity.
3Speed
If minimal capacitor values are used, then settling time decreases, but linearity deteriorates due to mismatch
Solution Approach 1:
The patent implements feedback by using the comparator to measure the actual capacitor values and comparing them against ideal values. Based on this feedback, the calibration logic adjusts the number of parallel unit capacitors for each capacitor element, creating a closed-loop system that ensures minimal capacitor values are used while maintaining linearity through continuous correction.
Solution Approach 2:
The calibration process performs preliminary adjustment of capacitor values before normal operation. By pre-setting the optimal capacitor configurations that minimize both size and mismatch, the system achieves fast settling times without sacrificing linearity during actual conversion operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances the linearity of the capacitive DAC, allowing for minimal capacitor values with faster settling times and improved ADC performance, maintaining the parasitic and non-ideal aspects of the capacitive DAC.
Implementation Method 1
A capacitive DAC consists of an array of capacitors with binary or non-binary weighted values. It employs the principle of charge redistribution to generate an analog output voltage during the binary search process.
Data Source
AI summary
Systems and methods are disclosed for Successive Approximation Register Analog-to-Digital Converter (SAR ADC) by coupling an ADC capacitive network coupled to a comparator; and performing binary search using a comparator output using a capacitive DAC calibration process to enhance SAR ADC linearity and performance. In one implementation, the calibration process starts with the least significant bit (LSB) capacitor calibration then proceed to higher bit capacitors until all the capacitors are calibrated. Each capacitor consists of fixed-value base capacitor and value-adjustable capacitor. The capacitor calibration logic is implemented based on the process then incorporated into SAR ADC. ADC performs capacitor calibration first before normal conversion operation. The non-ideal aspect of normal conversion operation is preserved and accounted during capacitor calibration. By employing capacitor calibration, the DAC capacitor value can be minimal to enhance settling and conversion rate, SAR ADC performance is improved.