Track-and-Hold Dither Injection for Interleaved ADC Mismatch
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Solution Overview
Problem
Designing high-speed track and hold (T/H) circuits for analog-to-digital converters (ADCs) is challenging due to issues with power consumption, noise, and performance, particularly in achieving timing and bandwidth matching across multiple channels in time-interleaved ADCs.
Innovation Solution
The implementation of a single high-speed T/H circuit driving multiple ADC slices, incorporating additive and multiplicative dither signals for calibration to address non-linearity, gain, and offset mismatches, while using switched-capacitor networks and amplifiers to improve signal-to-noise ratio and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple separate T/H circuits are used for each ADC slice in time-interleaved ADCs, then each channel can be independently optimized, but timing and bandwidth mismatches occur between channels
Solution Approach 1:
The patent merges multiple T/H circuits into a single shared T/H circuit that serves all ADC slices in the time-interleaved architecture. This consolidation eliminates timing and bandwidth mismatches between channels while reducing overall circuit complexity and component count.
2Measurement precision
If a single high-speed T/H circuit drives multiple ADC slices, then timing and bandwidth matching is improved, but the circuit must handle higher total bandwidth and drive capacity requirements
Solution Approach 1:
The patent implements dynamic switching mechanisms that allow the single T/H circuit to selectively connect to different ADC slices at different time intervals. This dynamic time-interleaved operation distributes the total bandwidth handling requirement over time, reducing the instantaneous power consumption and drive capacity demands on the circuit.
3Measurement precision
If dither signals are added for calibration, then non-linearity, gain, and offset mismatches are corrected, but circuit complexity and noise increase
Solution Approach 1:
The patent introduces dither signals as intermediary calibration inputs that are injected at specific points in the T/H circuit. These signals serve as mediators to excite and measure non-linearities, gain errors, and offset mismatches, enabling digital post-processing calibration without requiring complex analog correction circuits.
4Object-affected harmful factors
If switched-capacitor networks are used to improve signal-to-noise ratio, then noise performance is enhanced, but power consumption and circuit complexity increase
Solution Approach 1:
The patent employs switched-capacitor networks that operate in periodic sampling phases, where capacitors are charged during signal acquisition and then held or transferred during conversion phases. This periodic operation allows noise filtering through capacitive storage while consuming power only during switching transitions, rather than continuous power dissipation.
Data Source
AI summary
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.