TDC Calibration Circuit With Dynamic Delay Resolution Control
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face limitations in delay resolution at low voltage, low temperature, or slow corners due to degraded inverter performance, restricting their ability to achieve fine resolution and requiring a maximum DCO period for correct timing conversion, which is insensitive to process, voltage, and temperature (PVT) changes and input frequencies.
Innovation Solution
The implementation of a TDC circuit with multi-bit delay cells, counters, and decision logic circuits that dynamically adjust delay resolution by selecting active and inactive delay cells based on register values, allowing for optimization of delay resolution to cover at least one DCO period and remain insensitive to PVT and input frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a maximum DCO period is selected to ensure correct timing conversion, then the TDC can operate reliably, but the delay resolution becomes fixed and limited, resulting in much larger delay time than one DCO period when DCO frequency increases
Solution Approach 1:
The patent implements dynamic delay resolution adjustment by introducing a calibration circuit that automatically adjusts the delay cell configuration based on the actual DCO frequency. The system transitions from a fixed maximum DCO period to a dynamic adaptation mechanism where the delay resolution is continuously optimized to maintain approximately one DCO period total delay time, thereby resolving the contradiction between reliability and measurement precision.
Solution Approach 2:
The calibration circuit incorporates feedback mechanisms that monitor the DCO frequency and adjust the delay cell activation accordingly. The system uses feedback from the actual operating conditions to dynamically reconfigure the delay resolution, ensuring that the total delay time remains proportional to the DCO period regardless of frequency changes, thus maintaining both reliability and precision.
2Measurement precision
If delay resolution is increased to achieve finer timing measurement, then measurement precision improves, but the total delay time becomes much larger than one DCO period, requiring maximum DCO period selection
Solution Approach 1:
The system dynamically adjusts the number of active delay cells based on the DCO frequency to maintain an optimal balance between delay resolution and total delay time. By making the delay configuration adaptive rather than fixed, the system achieves fine resolution when needed while keeping the total delay time proportional to one DCO period, eliminating the need to select maximum DCO period.
Solution Approach 2:
The patent changes the operational parameters of the delay cells by dynamically adjusting which cells are active and their individual delay characteristics. This parameter adjustment allows the system to achieve fine delay resolution without proportionally increasing the total delay time, as the calibration circuit optimizes the distribution of delay across active cells based on real-time DCO frequency conditions.
3Device complexity
If conventional TDC design is used with fixed delay resolution, then device complexity is low, but the system becomes sensitive to PVT changes and input frequency variations
Solution Approach 1:
The calibration circuit introduces feedback loops that monitor PVT conditions and input frequency, then adjust the delay cell configuration accordingly. This feedback mechanism enables the TDC to automatically compensate for environmental variations and frequency changes, significantly improving adaptability without adding substantial complexity to the core TDC structure.
Solution Approach 2:
The system implements self-calibration capabilities where the TDC automatically adjusts its own delay resolution based on detected operating conditions. The calibration circuit performs self-service by monitoring system state and reconfiguring delay cells without external intervention, enabling the TDC to maintain optimal performance across varying PVT and frequency conditions while keeping the overall structure relatively simple.
Data Source
AI summary
Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.