Mixed-Signal DAC Switching Calibration for Low Third-Order Distortion
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Solution Overview
Problem
High-speed digital-to-analogue converters (DACs) face issues with third-order distortion due to parasitic capacitances and timing mismatches, which are exacerbated by miniaturization and reduced transistor sizes, leading to increased distortion and power consumption.
Innovation Solution
The proposed solution involves a modified differential switching circuit with four FETs per output node, operating in a repeating series of phases based on complementary clock signals, and a switch driver circuitry that uses time-interleaved data signals and mask signals to reduce the impact of data-dependent charge flow and timing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor size is reduced to increase conversion speed, then conversion frequency is improved, but third-order distortion increases due to parasitic capacitances
Solution Approach 1:
The switching circuit is divided into multiple independent switching units, each handling a portion of the total current. This segmentation reduces the parasitic capacitance impact on each individual switch, thereby reducing third-order distortion while maintaining high conversion frequency capability.
Solution Approach 2:
The invention changes the operating parameters of the switching circuit by using complementary clock signals with specific phase relationships and adjusting the switching timing to minimize the impact of parasitic capacitances, thereby reducing distortion at high conversion frequencies.
2Speed
If transistor size is reduced to increase conversion speed, then conversion frequency is improved, but power consumption increases
Solution Approach 1:
The current-steering DAC is divided into multiple segments with fewer current sources each, allowing the use of larger transistors in each segment which reduces power consumption while maintaining high conversion frequency through parallel operation.
3Device complexity
If conventional switching circuitry is used, then device complexity is low, but timing mismatches occur leading to distortion
Solution Approach 1:
The switching circuit uses preliminary actions by pre-charging and pre-discharging parasitic capacitances through complementary switching sequences, ensuring that timing mismatches are minimized before the actual current steering operation occurs.
Solution Approach 2:
The invention employs periodic complementary clock signals to drive the switching circuit, creating a regular periodic action that synchronizes the switching of multiple transistors and minimizes timing mismatches through consistent rhythmic operation.
Data Source
AI summary
A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.