SAR ADC Capacitive DAC Calibration for Mismatch Linearity
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Solution Overview
Problem
Capacitive DACs in Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) face linearity issues due to capacitor mismatch, which worsens with smaller capacitor values, affecting the ADC's performance and linearity.
Innovation Solution
A capacitive DAC calibration process is introduced, using a calibration capacitor to correct capacitor mismatch by incrementally adjusting the value of each capacitor during the binary search process, ensuring superior linearity without altering the normal conversion configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller capacitor values are used for faster DAC settling, then settling time is reduced, but capacitor mismatch worsens
Solution Approach 1:
The patent applies preliminary action by performing capacitor calibration before the actual ADC conversion process. The calibration process pre-adjusts the capacitor values to compensate for manufacturing mismatches, ensuring that even with smaller capacitor values for faster settling, the linearity is maintained through pre-corrected values.
Solution Approach 2:
The patent changes the capacitor values dynamically during calibration by adjusting the capacitance of individual capacitors based on measured mismatch errors. The calibration process modifies capacitor parameters (values) to optimize performance, allowing smaller capacitors to achieve both fast settling and acceptable linearity through value adjustment.
2Manufacturing precision
If capacitor calibration is performed to correct mismatch, then ADC linearity is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by designing a calibration system that automatically measures and corrects its own capacitor mismatches without external intervention. The calibration logic autonomously adjusts capacitor values based on internal measurements, reducing the need for external calibration equipment and simplifying the overall system complexity despite adding calibration functionality.
Solution Approach 2:
The calibration logic is designed to be universal and reusable across different capacitor arrays and ADC configurations. The same calibration methodology and logic can be applied to various capacitor sizes, bit resolutions, and ADC architectures, making the added complexity worthwhile through broad applicability and reusability.
3Loss of time
If minimal capacitor values are used, then settling time decreases, but linearity deteriorates due to mismatch
Solution Approach 1:
The patent uses preliminary action by pre-calibrating capacitor values before conversion. This allows the system to use minimal capacitor values for fast settling while the pre-applied calibration corrections maintain linearity, effectively decoupling the trade-off between speed and precision.
Solution Approach 2:
The calibration process implements feedback by measuring the actual capacitor values and using this information to adjust and correct the capacitor settings. This feedback mechanism ensures that minimal capacitor values can be used while maintaining linearity through continuous monitoring and adjustment based on actual performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The calibration process enhances ADC linearity and performance by allowing minimal capacitor values with faster settling times, maintaining the binary weighted capacitor characteristics and preserving the parasitic aspects, thus improving overall ADC performance.
Implementation Method 1
A capacitive DAC consists of an array of capacitors with binary or non-binary weighted values. It employs the principle of charge redistribution to generate an analog output voltage during the binary search process.
Data Source
AI summary
Systems and methods are disclosed for Successive Approximation Register Analog-to-Digital Converter (SAR ADC) by coupling an ADC capacitive network coupled to a comparator; and performing binary search using a comparator output using a capacitive DAC calibration process to enhance SAR ADC linearity and performance. In one implementation, the calibration process starts with the least significant bit (LSB) capacitor calibration then proceed to higher bit capacitors until all the capacitors are calibrated. Each capacitor consists of fixed-value base capacitor and value-adjustable capacitor. The capacitor calibration logic is implemented based on the process then incorporated into SAR ADC. ADC performs capacitor calibration first before normal conversion operation. The non-ideal aspect of normal conversion operation is preserved and accounted during capacitor calibration. By employing capacitor calibration, the DAC capacitor value can be minimal to enhance settling and conversion rate, SAR ADC performance is improved.