Time-Interleaved ADC Output Downsampling for Easier Testing
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Solution Overview
Problem
High-resolution and high-speed analog-to-digital converters (ADCs) require extensive hardware and complex measurement instruments due to increased pin count and data rate, making performance measurement difficult and costly.
Innovation Solution
A time-interleaved ADC device with multiple channels that performs down-sampling operations on quantization outputs to generate a digital signal with a lower frequency, reducing hardware requirements and measurement complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of ADC is increased, then the measurement precision is improved, but the number of pins required increases, resulting in larger circuit area
Solution Approach 1:
The patent divides the ADC system into multiple parallel channels (N channels), each with its own ADC circuitry. By segmenting the conversion task across multiple channels with fewer bits each, the system achieves high effective resolution while reducing the pin count per channel, thus lowering the overall circuit area requirement.
Solution Approach 2:
The patent transitions from a single-channel high-resolution ADC to a multi-channel time-interleaved architecture. This dimensional change from one high-bit converter to multiple lower-bit converters operating in parallel allows the system to achieve the same effective resolution with reduced pin complexity and smaller circuit area.
2Productivity
If the operating speed of ADC is increased, then the productivity is improved, but the data rate of converted digital signal increases, resulting in higher requirement of measurement instrument
Solution Approach 1:
The patent introduces a data combination circuit as an intermediary that processes the high-speed output signals from multiple channels. This intermediary performs downsampling and signal combination, converting the high-data-rate parallel outputs into a lower-rate composite signal that is easier to measure and analyze, thereby reducing the requirements for measurement instruments.
Solution Approach 2:
The patent creates multiple copies of the ADC circuitry operating in parallel at high speed, then combines their outputs. The data combination circuit effectively replicates and processes signals from each channel, allowing high operating speed to be maintained while the final combined signal has a manageable data rate for measurement purposes.
3Productivity
If multiple channels are used to increase operating speed, then the productivity is improved, but the hardware cost increases
Solution Approach 1:
The patent merges multiple channel outputs through a data combination circuit that performs downsampling and signal integration. By combining the outputs of N channels into a single composite signal, the system achieves high operating speed while reducing the overall hardware cost compared to using a single high-performance ADC, as lower-resolution ADCs are more cost-effective.
Data Source
AI summary
An analog-to-digital converter (ADC) device includes analog-to-digital converter circuitries and a data output circuitry. The ADC circuitries correspond to channels respectively, and convert an input signal to generate quantization outputs according to interleaved clock signals, wherein each of the interleaved clock signals has a sampling frequency. The data output circuitry performs a down-sampling operation according to a first control signal and the quantization outputs, in order to generate a digital signal. The first digital signal is for determining a performance of the ADC circuitries, and a frequency of the digital signal is N/M times of the sampling frequency, and N is a positive integer and is a number of the channels.