Multi-Stage ADC Calibration for Interleaving Error Correction
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Solution Overview
Problem
High-speed and high-accuracy analog-to-digital converters (ADCs) face challenges in designing due to speed and accuracy requirements, particularly in low power solutions, with time-interleaved stages prone to errors from clock skew, gain, and offset issues, leading to accuracy degradation in digital conversion.
Innovation Solution
The implementation of a multi-stage ADC architecture using a front-end multiplying digital-to-analog converter (MDAC) and an array of current-controlled ring oscillator (ICRO) sub-ADCs, with efficient calibration techniques to correct for non-linearities and errors, providing improved isolation and linearity, and allowing for scalable performance versus throughput trade-offs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved stages are used to achieve high sample rates, then speed is improved, but measurement precision deteriorates due to clock skew, gain, and offset errors
Solution Approach 1:
The ADC is divided into multiple time-interleaved sub-ADCs, each operating at a lower sample rate but contributing to the overall high sample rate through parallel processing. This segmentation allows the system to achieve high speed while managing precision requirements for each individual sub-ADC
Solution Approach 2:
A calibration mechanism is implemented that uses feedback from the digital outputs of the time-interleaved sub-ADCs to generate correction values. These correction values compensate for gain and offset errors, thereby maintaining measurement precision despite the use of multiple interleaved stages
2Productivity
If time-interleaved stages are used to achieve high sample rates, then productivity is improved, but manufacturing precision deteriorates due to tight clock skew control requirements
Solution Approach 1:
The calibration system automatically generates and applies correction values without requiring external manual adjustment. The system self-corrects for timing skew and gain/offset errors that arise during manufacturing, thereby maintaining high throughput without demanding extremely tight manufacturing tolerances
Solution Approach 2:
The calibration process dynamically adjusts correction parameters (gain and offset values) based on actual operating conditions and measured errors. This allows the system to adapt to manufacturing variations and maintain high productivity without requiring perfect manufacturing precision
3Measurement precision
If calibration is performed to correct gain and offset errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The calibration logic is designed to perform multiple functions: it corrects gain errors, offset errors, and timing skew effects simultaneously using a unified correction mechanism. This multi-functionality reduces the need for separate calibration circuits for each error type, thereby limiting the increase in device complexity
4Productivity
If high-speed operation is implemented, then productivity is improved, but use of energy increases
Solution Approach 1:
The high-speed conversion task is divided among multiple time-interleaved sub-ADCs, allowing each sub-ADC to operate at a manageable speed while collectively achieving the desired high sample rate. This distribution of workload helps control power consumption compared to a single high-speed converter
Solution Approach 2:
The calibration process is implemented periodically rather than continuously, reducing the energy overhead associated with calibration operations. The system alternates between normal high-speed conversion and calibration phases, maintaining productivity while managing power consumption
Data Source
AI summary
Digital calibration systems and related methods are disclosed for multi-stage analog-to-digital converters (ADCs). For one embodiment, a multi-stage ADC includes an initial ADC, an additional ADC, and calibration logic. The initial ADC generates an output signal and N-bit digital values that are based upon an input signal. The additional ADC receives the output signal from the initial ADC and generates M-bit digital values that are based upon the output signal. The calibration logic receives the N-bit digital values and the M-bit digital values and generates correction values. The correction values are based upon differences between maximum values and minimum values for M-bit digital values associated with different regions determined by the N-bit digital values. Digital conversion outputs for the multi-stage ADC are provided as combinations of the N-bit digital values and the M-bit digital values corrected with the correction values.