Current-Controlled MDAC for Time-Interleaved ADC Accuracy
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Solution Overview
Problem
High-speed and high-accuracy analog-to-digital converters (ADCs) face challenges in designing due to speed and accuracy requirements, particularly for low power solutions, with time-interleaved stages prone to errors from clock skew, gain, and offset issues, leading to accuracy degradation in digital conversion.
Innovation Solution
The implementation of a multi-stage ADC architecture using a front-end multiplying digital-to-analog converter (MDAC) and an array of current-controlled ring oscillator (ICRO) sub-ADCs, with efficient calibration techniques to correct for non-linearities and errors, reducing the resolution requirements and improving isolation and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved stages are used to achieve high sample rates, then speed is improved, but measurement precision deteriorates due to clock skew, gain, and offset errors
Solution Approach 1:
The ADC is divided into multiple time-interleaved sub-ADCs that operate in parallel, each handling a portion of the sampling process. This segmentation enables high sample rates while the patent addresses the resulting precision issues through calibration techniques that correct for the errors introduced by dividing the system into multiple channels.
Solution Approach 2:
The patent implements calibration mechanisms that measure and correct for clock skew, gain, and offset errors in the time-interleaved stages. This feedback approach continuously monitors and adjusts the system to maintain measurement precision despite the speed advantages gained from time-interleaved architecture.
2Productivity
If time-interleaved stages are used to increase throughput, then productivity is improved, but manufacturing precision deteriorates due to difficulties in controlling clock skew and gain/offset errors
Solution Approach 1:
The patent performs calibration operations during manufacturing and operation to pre-establish correct timing and gain/offset relationships between time-interleaved stages. This preliminary action compensates for manufacturing variations and ensures that clock skew and gain/offset errors are corrected before they affect normal high-throughput operation.
Solution Approach 2:
The calibration process adjusts critical parameters such as clock timing, gain, and offset for each time-interleaved stage to optimize performance. By dynamically changing these parameters based on measured errors, the system achieves both high throughput and maintains manufacturing precision despite process variations.
3Speed
If multiple time-interleaved stages are implemented to achieve high sample rates, then device complexity increases, but reliability deteriorates due to susceptibility to sampling errors and spurious noise
Solution Approach 1:
The patent implements comprehensive calibration and correction mechanisms that continuously monitor for sampling errors, gain/offset mismatches, and spurious noise in the time-interleaved stages. This feedback system detects and corrects reliability-degrading issues, maintaining output spectrum quality despite the increased complexity of multiple parallel stages.
Solution Approach 2:
The patent transforms the potential harm of clock skew and gain/offset errors into beneficial correction opportunities by implementing calibration routines that deliberately measure these errors and apply compensating adjustments. What would normally be harmful effects are converted into measurable parameters that can be corrected, thereby improving reliability.
Data Source
AI summary
Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit can include a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.