Asynchronous Upsizing Circuit Buffer Sharing
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Solution Overview
Problem
In mobile systems, the asynchronous bridge and upsizer circuits face challenges in maintaining high 'read ready' signals due to bandwidth differences, leading to performance degradation and increased gate count overhead, particularly during burst write operations, which affects the efficiency of channel compaction and bus utility.
Innovation Solution
An asynchronous upsizing circuit is introduced, featuring a write buffer and read buffer with asynchronous packing and unpacking controllers, operating on different clocks to optimize channel compaction during burst operations, reducing gate count overhead and improving latency and bus utility by sharing buffers and adjusting clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate async bridge and upsizer circuits are used, then bandwidth matching between CPU and bus system is achieved, but gate count overhead increases and channel compaction efficiency decreases
Solution Approach 1:
The patent combines the async bridge function and upsizer function into a single integrated circuit. The async bridge handles clock domain crossing between CPU and bus system, while the upsizer performs data width expansion from 64-bit to 128-bit. By merging these two separate circuits into one, the patent reduces gate count overhead and improves channel compaction efficiency without sacrificing bandwidth matching capability.
2Reliability
If buffers are added to maintain high read ready signal, then memory controller operation continues, but gate count overhead increases
Solution Approach 1:
The integrated circuit performs multiple functions: async bridge operation, data upsizing, channel compaction, and read ready signal maintenance. By designing a universal circuit that handles all these functions, the patent avoids adding separate buffers and control logic that would increase gate count overhead, while still maintaining reliable read ready signal operation.
3Productivity
If CPU operates at high frequency with wide data bus, then processing performance improves, but bus system frequency must be reduced to match bandwidth
Solution Approach 1:
The patent changes the data width parameter from 64-bit to 128-bit in the upsizer portion of the integrated circuit. This parameter change allows the CPU to operate at high frequency with its native 64-bit bus, while the upsizer expands the data to 128-bit for the bus system, effectively decoupling the frequency requirements and allowing the CPU to maintain high processing performance without being constrained by bus frequency limitations.
Data Source
AI summary
An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.