Generating/Distributing Signals TRIZ Cases
- Asynchronous FIFO Pointer Offset for Clock Domain Crossing
Processor adjusts read and write pointers using frequency ratios to minimize latency while maintaining data integrity across clock domains.
- Clock Distribution System Configuration for IC Power Optimization
A clock distribution system selects configurations based on demand indications to optimize energy efficiency.
- Interconnect Fabric Frequency Transition via Clock Stalling
Clock stalling transitions interconnect fabric frequency without interrupting agents, resolving the trade-off between power efficiency and continuous operation.
- Guest Timer Facility for Virtualized Processing Systems
A guest timer facility generates local PM Timer values from the Time Stamp Counter to eliminate virtual machine monitor overhead.
- Post-CTS Clock Tree Skew Reduction via Target Delay Reformulation
A post-CTS clock tree modification system sets target insertion delays based on mean sink values to reduce skew violations.
- Clock Stuttering to Reduce Voltage Ringing in Synchronous Systems
Skipping clock transitions during transient periods reduces voltage ringing magnitude and duration, preventing data errors without increasing power consumption.
- PCIe SRIS Mode Selection via Dynamic Clocking Control
Dynamic SRIS mode selection resolves vendor compatibility conflicts by switching clocking configurations at runtime based on link training outcomes.
- Low Power Clock Multiplexer for MCU Power Domain Management
A low power clock multiplexer fans out a source clock signal to multiple input output groups within a microcontroller unit.
- Configurable Transmitter Timer Circuit for Data Rate Adaptation
A configurable timer circuit adjusts input data timing using retimers and multiplexors to support serial transmission.
- Leap Second Handling in Time Synchronization Systems
A time synchronization system exposes leap seconds to applications through distinct conversion components.
- Peripheral Timebase Synchronization Across Clock Domains
A peripheral interface circuit maintains a local timebase correlated to a global host timebase using phase and frequency detection.
- Storage Array Cyber Recovery Orchestration
An orchestration layer manages connectivity access between host devices and recovery arrays to resolve logical corruption from ransomware attacks.
- Bidirectional CS Line for Interrupt Management
Bidirectional chip select lines merge slave selection with interrupt transmission to eliminate dedicated pins and reduce wiring complexity.
- SoC Clock Management Circuitry Hardware Control
A clock management circuitry uses master and slave controllers connected via dedicated channels to handle signal distribution.
- Master Slave Touch Controller Segmentation for Large Panels
Segmenting touch sensing into master and slave controllers distributes workload to overcome single ASIC limitations on large panels.