Interconnect Fabric Frequency Transition via Clock Stalling
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Solution Overview
Problem
Current power management in integrated circuits faces challenges in efficiently transitioning the frequency of interconnect fabrics, managing power delivery to optimize battery life, and accurately measuring sleep state exit latency, while also dealing with limitations in maximal current and voltage capabilities, which can restrict CPU performance and lead to increased power consumption.
Innovation Solution
The solution involves a hardware and software approach that allows seamless frequency transitions in interconnect fabrics without interrupting agents, dynamic voltage control to optimize power delivery, accurate measurement and reporting of sleep state latency, and non-blocking power interfaces to manage maximal current and voltage within the capabilities of power management agents, ensuring efficient power distribution and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the frequency of interconnect fabric is changed to optimize power consumption, then power efficiency is improved, but the transition may interrupt agents using the fabric
Solution Approach 1:
The system dynamically adjusts the frequency of the interconnect fabric based on power consumption requirements. The frequency can be changed between different operating modes (e.g., high frequency for performance, low frequency for power savings) while maintaining continuous operation through proper clock domain crossing mechanisms that allow agents to operate asynchronously across frequency transitions.
Solution Approach 2:
The patent introduces intermediary mechanisms including clock controllers and frequency synthesizers that mediate between different frequency domains. These intermediaries enable seamless frequency transitions by buffering and synchronizing signals, allowing agents to continue operating without interruption during frequency changes.
2Duration of action of moving object
If dynamic voltage control is implemented to optimize power delivery, then battery life is extended, but measurement of sleep state exit latency becomes more complex
Solution Approach 1:
The system performs preliminary measurements of sleep state exit latency during normal operation before entering deep sleep modes. By collecting latency data in advance and storing it in lookup tables or databases, the system can use this pre-measured information to guide future sleep state transitions, extending battery life without requiring complex real-time measurement during actual sleep transitions.
Solution Approach 2:
The patent implements feedback mechanisms where the system monitors actual sleep state exit latency and uses this information to adjust voltage and frequency settings. This feedback loop allows the system to optimize power delivery by learning from actual performance data, extending battery life while managing measurement complexity through systematic data collection and analysis.
3Power
If maximal current and voltage limits are enforced by power management agents, then power delivery is optimized, but CPU performance is restricted
Solution Approach 1:
The system dynamically adjusts voltage and current limits based on real-time power management requirements. Power management agents can enforce maximal current and voltage limits during high-performance scenarios, then reduce these limits during power-saving modes. This dynamic adjustment allows the system to optimize both power delivery and CPU performance according to actual operational needs rather than being constrained by fixed limits.
Solution Approach 2:
The patent changes key parameters including voltage, current limits, and frequency thresholds based on power management policies. By adjusting these parameters dynamically, the system can enforce stricter power limits when battery life is critical, then relax them when performance is needed. This parameter flexibility allows optimization of both power delivery efficiency and CPU performance without being locked into fixed constraints.
Data Source
AI summary
Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.