Post-CTS Clock Tree Skew Reduction via Target Delay Reformulation
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Solution Overview
Problem
Current clock tree synthesis (CTS) techniques are labor-intensive and difficult to modify post-synthesis, as changes to one clock sink can impact other sinks, leading to design rule violations and increased power consumption, necessitating improved methods for post-CTS clock tree modifications that reduce the number of necessary physical modifications and eliminate design parameter violations.
Innovation Solution
Implementing a system that automatically modifies post-CTS clock trees by setting target insertion delays based on mean insertion delays, identifying sinks requiring adjustment, and reducing target insertion delay adjustments to eliminate skew and insertion delay violations without requiring designer input or reperforming CTS, thereby minimizing physical modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual modifications are made to a synthesized clock tree, then design parameter violations can be corrected, but the process becomes labor-intensive and time-consuming
Solution Approach 1:
The system automatically detects design parameter violations and performs corrections without requiring manual designer intervention. The automated system identifies sinks with violations, calculates appropriate delay adjustments, and modifies the clock tree structure autonomously, eliminating the labor-intensive manual modification process while maintaining design parameter compliance.
Solution Approach 2:
The system continuously monitors clock tree performance by calculating insertion delays and skew values, compares them against target parameters, and automatically adjusts the clock tree structure in response to detected violations. This closed-loop feedback mechanism ensures design parameter compliance while minimizing manual intervention and reduction modification time.
2Manufacturing precision
If modifications are made to one clock sink, then that sink's performance improves, but other sinks may experience design rule violations
Solution Approach 1:
The system segments the clock tree modification process by identifying and treating individual sinks with violations separately. Each sink is analyzed independently to determine its specific delay adjustment requirements, allowing precise local modifications that improve that sink's timing without inadvertently affecting other sinks' compliance. This granular approach prevents cascading design rule violations.
Solution Approach 2:
The system applies localized delay adjustments to specific clock sinks based on their individual timing requirements. By calculating and applying targeted delay modifications only where needed rather than global changes, the system improves specific sink performance while maintaining design rule compliance across the entire clock tree, preventing ripple effects that could cause other sinks to violate design rules.
3Reliability
If extensive modifications are made to the clock tree, then timing violations are corrected, but power consumption increases
Solution Approach 1:
The system performs only the minimum necessary modifications to correct timing violations rather than comprehensive re-optimization of the entire clock tree. By identifying and addressing only the specific sinks with violations and applying precise delay adjustments to those areas, the system eliminates timing violations while minimizing the scope of modifications and associated power consumption increases.
4Manufacturing precision
If the clock tree is re-synthesized to fix violations, then design parameters are corrected, but the process is difficult and time-consuming
Solution Approach 1:
The system performs preliminary analysis of the clock tree to identify sinks with design parameter violations before making modifications. By pre-calculating insertion delays, determining which sinks violate design rules, and planning appropriate delay adjustments in advance, the system streamlines the correction process and avoids time-consuming trial-and-error re-synthesis iterations.
Data Source
AI summary
Methods and systems for performing post clock tree synthesis (CTS) of a clock tree include accessing, from memory, an integrated circuit design comprising a clock tree interconnecting a clock source to a plurality of clock sinks. Each clock sink has an associated current insertion delay. A mean insertion delay of the plurality of clock sinks is determined based on the associated current insertion delays of the clock sinks. A target insertion delay for the clock sinks is set based on the mean insertion delay and a target insertion delay adjustment determined for each individual clock sink. One or more clock sinks are identified that have a target insertion delay adjustment exceeding a skew threshold value. The clock tree is modified to reduce the target insertion delay adjustment, for each identified clock sink of the one or more clock sinks, to less than or equal to the skew threshold value.