Low Power Clock Multiplexer for MCU Power Domain Management

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Solution Overview

Problem

Computing devices with multiple power domains and clock domains face increased bill of materials (BOM) costs and PCB complexity due to the need for separate low power clock sources for each power domain, which also occupy valuable space on the printed circuit board (PCB).

Innovation Solution

An electronic circuit within a microcontroller unit (MCU) generates multiple clock signals from a source clock signal and fans them out to multiple power domains, reducing the number of required clock sources by distributing these signals to input/output groups corresponding to different power domains, thereby simplifying clock domain management and reducing BOM costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate low power clock sources are used for each power domain, then power management reliability is improved, but device complexity and BOM costs increase

Engineering Contradiction:
Improvepower management reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The main clock source is designed to serve multiple power domains simultaneously by providing clock signals to both the first set of peripherals in the first power domain and the second set of peripherals in the second power domain. This multi-functional approach eliminates the need for separate dedicated clock sources for each power domain, reducing device complexity and BOM costs while maintaining reliable power management across all domains.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate low power clock sources are used for each power domain, then power management reliability is improved, but PCB area increases

Engineering Contradiction:
Improvepower management reliabilityVSAvoidPCB area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple clock source functions are merged into a single main clock source that can distribute clock signals to multiple power domains. This consolidation reduces the number of discrete clock source components required on the PCB, thereby reducing the total PCB area occupied by clock source components while maintaining the ability to independently manage power domains.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple low power clock sources are used, then power domain independence is improved, but BOM costs increase

Engineering Contradiction:
Improvepower domain independenceVSAvoidBOM costs
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The main clock source is configured to provide clock signals to multiple power domains, making it a universal clock source that replaces multiple specialized low power clock sources. This approach maintains the independence and configurability of each power domain while significantly reducing the number of components required, thereby lowering BOM costs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If multiple low power clock sources are used, then power domain independence is improved, but device complexity increases

Engineering Contradiction:
Improvepower domain independenceVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system implements dynamic clock domain management where the main clock source can be selectively enabled or disabled for different power domains based on operational requirements. The clock controller dynamically configures which peripherals receive clock signals from the main clock source, allowing flexible power domain independence without requiring multiple static clock source components, thus reducing device complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240419209A1Low power clock multiplexer in microcontroller with selectable power domain output
Publication Date: 2024.12.19 INFINEON TECHNOLOGIES AMERICAS CORP
  • US20240419209A1 patent drawing
  • US20240419209A1 patent drawing
  • US20240419209A1 patent drawing

AI summary

Systems and methods described herein fan out a source clock signal within the MCU to produce a plurality of clock signals. The systems and methods distribute the plurality of clock signals to a plurality of input/output (I/O) groups within the MCU, wherein each of the plurality of VO groups correspond to a different one of a plurality of power domains of the MCU. The systems and method provide the plurality of clock signals to a plurality of peripherals coupled to the plurality of I/O groups.