PCIe SRIS Mode Selection via Dynamic Clocking Control
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Solution Overview
Problem
The existing PCIe technologies face challenges in dynamically selecting and changing the SRIS mode operation, which is essential for optimizing clocking modes in interconnects, especially when dealing with different vendor implementations and the need for flexible clocking configurations in systems with varying devices.
Innovation Solution
The introduction of a mechanism that allows system software to determine and control the SRIS mode selection through specific registers, enabling runtime changes based on link conditions and device compatibility, ensuring seamless operation across different PCIe components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed clocking mode is used in PCIe interconnects, then device compatibility is simplified, but adaptability to different vendor implementations and link conditions deteriorates
Solution Approach 1:
The patent implements dynamic clocking mode selection by introducing a mechanism that allows the PCIe system to switch between different clocking modes (SSC and non-SSC) at runtime based on link conditions and device compatibility. The clocking mode is no longer fixed but can be changed dynamically through link retraining sequences, enabling the system to adapt to different vendor implementations while maintaining manageable complexity through automated selection logic.
Solution Approach 2:
The patent changes the clocking parameter from a fixed value to a variable that can be adjusted based on system conditions. By allowing the clocking mode parameter to change between SSC and non-SSC modes depending on link training outcomes and device compatibility, the system achieves adaptability to different vendor implementations without requiring complex manual configuration for each scenario.
2Adaptability or versatility
If SRIS mode selection is made dynamic and controllable via registers, then flexibility and adaptability improve, but system complexity increases
Solution Approach 1:
The patent implements self-service by enabling the PCIe system to automatically select and configure the appropriate SRIS mode through register-controlled link retraining sequences. The system monitors link conditions and device compatibility, then autonomously adjusts the clocking mode without requiring manual intervention, thereby achieving flexibility while keeping the control mechanism manageable through automated decision-making logic.
Solution Approach 2:
The patent incorporates feedback mechanisms where the system monitors link training outcomes and device compatibility information, then uses this feedback to dynamically adjust the SRIS mode selection. The register control mechanism receives feedback about link conditions and automatically modifies the clocking configuration accordingly, providing flexibility while maintaining manageable complexity through closed-loop control.
3Use of energy by moving object
If clocking modes are optimized for specific devices, then energy efficiency improves, but interoperability across different vendors deteriorates
Solution Approach 1:
The patent implements dynamic clocking mode selection that allows the system to switch between energy-efficient SSC mode and compatible non-SSC mode based on vendor implementation and link conditions. By making the clocking mode dynamic rather than fixed, the system can optimize energy efficiency when SSC is supported while maintaining interoperability with vendors that implement non-SSC clocking, thus resolving the contradiction between energy efficiency and interoperability.
Solution Approach 2:
The patent changes the clocking mode parameter dynamically based on vendor compatibility and link training outcomes. When link training succeeds in SSC mode, the system maintains the energy-efficient configuration; when compatibility issues arise, the system transitions to non-SSC mode. This parameter change mechanism enables the system to achieve energy efficiency optimization while preserving interoperability across different vendor implementations.
Data Source
AI summary
Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.