Clock Stuttering to Reduce Voltage Ringing in Synchronous Systems
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Solution Overview
Problem
Stopping and starting clock signals in computer systems causes transient voltage fluctuations due to complex power delivery networks, leading to decreased timing margins and data errors, which can be detrimental to system performance, especially in portable devices where power conservation is crucial.
Innovation Solution
Implementing a modified timing signal, known as clock stuttering, by skipping clock transitions during transient periods, such as clock-starting events, to reduce voltage ringing and stabilize power delivery networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signals are stopped to save power, then power consumption is reduced, but transient voltage fluctuations occur when clock signals are restarted
Solution Approach 1:
The patent applies preliminary action by gradually ramping up the clock signal frequency from zero to the target frequency over a predetermined time period before fully activating the clock domain. This gradual activation prevents sudden current demands that cause voltage fluctuations, thereby maintaining voltage stability while still achieving power savings through selective clock gating.
Solution Approach 2:
The patent implements dynamics by making the clock signal frequency variable during the activation process. Instead of a fixed immediate transition, the clock frequency dynamically changes over time, starting at zero and incrementally increasing to the target frequency. This dynamic approach allows the system to adapt to power delivery network conditions and avoid transient voltage drops.
2Productivity
If clock signals are restarted immediately to maintain performance, then system responsiveness is improved, but voltage ringing and data errors increase
Solution Approach 1:
The patent applies preliminary action by performing a gradual frequency ramp-up sequence before full clock activation. This preliminary gradual activation prepares the power delivery network for the increasing current demand, preventing voltage ringing and glitches that would occur with immediate full-power clock activation, thereby eliminating data errors without significant performance penalty.
Solution Approach 2:
The patent implements periodic action through the use of a predetermined time period for the frequency ramp-up process. The clock frequency increases in a controlled periodic manner over this specified duration, allowing the power delivery network to settle at each frequency step. This periodic approach balances system responsiveness with voltage stability by controlling the rate of change rather than allowing immediate activation.
3Reliability
If waiting time is extended for voltage fluctuations to diminish, then voltage stability is improved, but system performance deteriorates
Solution Approach 1:
The patent applies preliminary action by proactively managing the clock activation process through gradual frequency ramping. Instead of waiting passively for voltage fluctuations to diminish after activation, the system performs the stabilizing action during the activation process itself. This eliminates the need for extended waiting periods while maintaining voltage stability, thereby resolving the time-performance tradeoff.
Solution Approach 2:
The patent implements continuity of useful action by maintaining system operation throughout the clock activation process. The gradual frequency ramp-up allows the system to remain functional at reduced clock speeds during activation rather than halting operation entirely. This continuous operation maintains system performance while achieving voltage stability, eliminating the need to extend waiting time at the expense of performance.
Data Source
AI summary
The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.