Asynchronous Binary-Search ADC with Hierarchical Comparator Tree
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Solution Overview
Problem
Current analog-to-digital converters face high power consumption due to the large number of comparators required in flash architectures, especially as resolution increases, which is a challenge in achieving efficient medium- to high-speed and low-resolution conversions.
Innovation Solution
The Comparator-based Asynchronous Binary Search (CABS) architecture structures comparators in a hierarchical tree, where only dynamic comparators with embedded thresholds are active, and the clock signal is applied to the root comparator, reducing the number of active comparators and power consumption by using a binary search instead of a parallel search.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash architecture is used to achieve high-speed conversion, then conversion speed is improved, but power consumption increases exponentially with resolution
Solution Approach 1:
The patent segments the parallel search process of flash architecture into a hierarchical binary search structure. Instead of all comparators operating simultaneously, the search is divided into multiple levels where comparators are activated sequentially based on previous comparison results. This segmentation reduces the number of active comparators at any given time, thereby reducing power consumption while maintaining conversion speed through the hierarchical structure.
Solution Approach 2:
The patent introduces dynamic activation of comparators based on the search progress. The hierarchical binary search structure allows comparators to be dynamically enabled or disabled depending on the current search state. This dynamic operation reduces the average number of active comparators compared to static flash architecture, achieving lower power consumption while maintaining high-speed conversion capability.
2Use of energy by moving object
If the number of comparators is reduced to lower power consumption, then power consumption is improved, but measurement precision may deteriorate
Solution Approach 1:
The patent transforms the traditional two-dimensional parallel comparator array into a multi-level hierarchical structure. By adding the temporal dimension through sequential activation and organizing comparators in a tree structure with multiple levels, the system achieves the same measurement precision with fewer simultaneously active comparators. The hierarchical levels ensure that all necessary comparison points are covered while reducing peak power consumption.
3Speed
If parallel search is used to determine bits quickly, then conversion speed is improved, but device complexity increases due to large number of comparators
Solution Approach 1:
The patent segments the bit determination process into hierarchical levels, where each level handles specific bit positions. This segmentation reduces the number of comparators needed at each stage compared to full parallel search, while the hierarchical structure ensures that bit determination remains efficient. The binary search approach divides the search space systematically, reducing overall device complexity.
Data Source
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AI summary
The present invention is related to an analog-to-digital converter circuit (1) wherein a comparator based asynchronous binary search is used. The architecture comprises a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator (2) only, preferably to the first or root comparator. The at least one comparator (2) is further arranged for controlling at least one other comparator (3) of the plurality of comparators (2, 3, 4).