Power Saving Provisions TRIZ Cases

A fast local feedback path with a differentiator compensates excess loop delay in CTDSMs, improving stability, SNR, and power efficiency.

Hybrid switched current cells cut high-frequency DAC memory effects and distortion without the die size or power penalties of conventional fixes.

By removing high-impedance output switches and using channel control signals, the circuit cuts display power, heat, and area.

A two-phase capacitance conversion circuit combines charge balancing with residual voltage ADC to deliver fast, precise digital measurement.

Selective micro-current source activation in a thermometer-coded DAC cuts energy use while preserving output range and signal fidelity.

Complementary parallel switching in tri-level DAC unit elements reduces data-dependent ISI and kickback without major area or power penalties.

Gain-compensated path switching in a multi-path analog front end reduces ADC artifacts while extending dynamic range and power efficiency.

A reconfigurable RC circuit lets a DAC calibrate mismatch errors without a separate high-accuracy ADC, cutting area and power use.

A delayed clock engages larger capacitor groups after early bit decisions, cutting ADC power draw while preserving noise sensitivity.

Dual DAC switching lets a differential ADC sample single-ended inputs directly, avoiding extra conversion circuitry, power, area, and delay.

Calibration sets ADC and DAC compensation characteristics to cancel converter nonlinearity while reducing chip area and power.

Mode-switched ADC cells adjust input ranges and clock phases to match speed and accuracy needs while avoiding unnecessary power use.

Segmented electrodes driven by multi-bit actuation improve optical DAC linearity and dynamic range for high-bandwidth signal conversion.

Non-power-of-two electrode weighting linearizes Mach-Zehnder optical DAC output, improving dynamic range and resolution.

Thermally coupled heating resistors and an inverted measuring voltage keep A/D converter power loss constant, reducing temperature-driven errors.

Dynamic bias-current control tracks sampling-rate changes to cut analog power in mixed-signal circuits while preserving signal quality.

A trigger-driven clock-halting circuit pauses ADC conversion during SMPS noise windows, preserving sampling rate while reducing area and power.

Closed-loop tuning of a feedback resistor from sensed shunt current speeds reference settling while lowering OTA power in pipelined ADCs.

A shunt-capacitor OTA buffer keeps ADC reference voltages stable under switched-capacitor loading while cutting power demand.

High current is applied only during switching, cutting discrete-time amplifier power use during non-switching periods.

Capacitor arrays and switch control let a SAR ADC amplify and convert signals without an active PGA, cutting power and circuit cost.

Low-voltage conversion switches cut SAR ADC level-shifting power, area, and current spikes while preserving settling speed and signal quality.

A filtered, switchable ADC clock enables higher-Nyquist IF sampling with lower noise floor and wider bandwidth in synthetic instruments.

A hierarchical self-clocked comparator tree cuts active comparator count and ADC power while preserving fast binary-search conversion.

Rearranged folding blocks cut differential and load circuit count, reducing ADC current draw, bulk, and speed limits.

A self-clocked binary-search comparator tree reduces ADC power by activating only needed comparators while maintaining fast conversion.

A reduced-cell anti-aliasing folding ADC structure cuts current and area while preserving folding-curve regularity and high-speed conversion.

Selective current-source sleep control in a folding ADC cuts power use while preserving accurate analog signal conversion.

Multiple modulator electrodes are driven from combined input bits to linearize Mach-Zehnder optical DAC output and extend dynamic range.

Selective comparator activation narrows the flash ADC window by signal change rate, cutting power while preserving high-speed sampling.

By gating ring VCO oscillation to each sampling cycle, this ADC cuts redundant switching while preserving resolution and first-order noise shaping.

An impedance-based ADC temperature sensor replaces auxiliary BJT circuits to improve accuracy while cutting area, power use, and cost.

Bias-controlled PMOS and NMOS termination transistors let a DAC match line impedance while cutting passive termination power loss.

Adaptive bit-depth cuts A/D comparisons during limited-range signal cycles, reducing power and conversion time in implantable monitors.

A two-latch capture scheme switches only at comparator trip, cutting power, noise, crosstalk, and linearity issues in single-slope ADCs.

An adjusting circuit preserves ideal secondary divider voltage in a dual-string DAC while removing op-amp isolation, cutting area, power, and settling time.

A flash ADC handles coarse MSBs while parallel SAR channels refine and verify LSBs to raise conversion speed without the usual power penalty.

Complementary parallel switches create a periodic baseline of activity in tri-level DAC elements, reducing ISI at higher frequencies.

A global clock and SHA-less sampling lanes cut clock skew, power draw, and distortion in high-speed pipelined ADCs.

Comparator subsets split across input ranges cut ADC quantizer power while preserving resolution and SNDR in continuous-time sigma-delta converters.

Multiple independently driven electrodes linearize Mach-Zehnder optical DAC response, extending dynamic range for high-bandwidth analog conversion.

Sequential capacitor switching and comparator stages raise image sensor ADC bit accuracy while limiting circuit area and power use.

A hierarchical pipelined ADC uses tunable thresholds and staged amplification to cut power and input capacitance while correcting nonlinear distortion.

Coarse measurement activates only the needed fine comparators in a flash ADC, cutting power dissipation without sacrificing conversion speed.

Dynamic bias current ramping lets a two-stage single-slope ADC keep high conversion accuracy while cutting average power use.

Switched-capacitor voltage transformers cut amplifier noise in a hearing aid delta-sigma converter while keeping current consumption low.

Tunable thresholds in a hierarchical pipelined ADC cut power and input capacitance while correcting non-linear distortion.

Control circuitry shifts the amplifier output-stage supply so a DAC can span a wider voltage range while keeping power dissipation low.

Switched-capacitor voltage transformers raise input and feedback voltages to cut amplifier noise and current draw in hearing aid ADCs.

Idle bias current keeps an ADC ready between samples, cutting battery drain while avoiding startup delay when conversion is needed.