Two-Stage Single-Slope ADC With Dynamic Bias Current Control
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Solution Overview
Problem
High-resolution analog to digital conversion in image sensors requires high clock speeds and increased power consumption, making it challenging to meet the demands of high-definition video processing while maintaining low power consumption.
Innovation Solution
A two-stage analog to digital converter (ADC) design that generates most significant bits in the first stage and least significant bits in the second stage, with a bump bias generator that adjusts bias current based on the clock cycle segments to reduce power consumption, allowing for high accuracy at peak power requirements while minimizing average power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high clock speeds are used for high-resolution analog to digital conversion, then conversion speed and resolution are improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the bias current adjustable and time-varying. The bump bias generator dynamically changes the bias current level based on the operational phase: providing high current during conversion for fast settling, then reducing current during hold phase to save power. This dynamic adaptation resolves the contradiction between maintaining high conversion speed and reducing power consumption.
Solution Approach 2:
The patent implements periodic action through the two-stage conversion process with distinct phases. The first stage performs rapid conversion at high bias current, then the system transitions to a hold phase with reduced bias current. This periodic switching between high-performance and low-power modes allows the system to achieve high conversion speeds when needed while minimizing power consumption during stable operation.
2Measurement precision
If bias current is increased to maintain high accuracy during conversion, then measurement precision is improved, but average power consumption increases
Solution Approach 1:
The patent segments the conversion process into two distinct stages: a conversion phase requiring high accuracy and a hold phase where accuracy is maintained but power consumption should be reduced. By separating these functions temporally and providing different bias current levels for each stage, the system achieves high measurement precision during conversion while minimizing average power consumption during the hold phase.
Solution Approach 2:
The patent applies partial action by providing excessive bias current only during the necessary conversion phase when high accuracy is critical, then reducing to minimal sufficient current during the hold phase. This ensures measurement precision is maintained when needed without the penalty of continuously high power consumption, achieving optimal balance between accuracy and power efficiency.
Data Source
AI summary
Providing for a two-stage single-slope analog to digital converter (ADC) exhibiting high resolution in conjunction with reduced power consumption is described herein. The ADC can achieve a digital resolution of at least 13 bits according to one or more disclosed embodiments, with significantly lower power consumption than conventional high resolution analog to digital converters. In operation, bias current supplied to one or more components of the ADC can be ramped up to a high magnitude during high accuracy or high speed processes of the ADC. Upon completion of these processes, the bias current can be sharply reduced for at least a portion of a clock cycle. During a residue amplification process associated with a second stage of the ADC, bias current can be increased to a moderate level. Average power consumption can be reduced significantly, while maintaining peak power requirements.