Interleaved Pipelined ADC with Tunable Threshold Calibration
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Solution Overview
Problem
Existing low-resolution, high-speed analog-to-digital converters face challenges with high power consumption and large input capacitance due to traditional architectures, which limit their efficiency in applications like hard disk read channels and wideband wireless standards.
Innovation Solution
A pipelined analog-to-digital converter with a hierarchical tree structure of comparing means and amplifying circuits, where thresholds are tunable and calibrated to remove non-linear distortion, using a binary search algorithm to reduce the number of active comparators and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional time-interleaved SAR architecture is used to achieve high-speed conversion, then sampling frequency increases, but input capacitance becomes 10-20 times larger
Solution Approach 1:
The converter is divided into multiple parallel channels, each operating at a lower sampling frequency but contributing to the overall high-speed conversion. This segmentation allows the system to achieve high effective sampling frequency while each individual channel maintains lower capacitance requirements
Solution Approach 2:
The patent transitions from a single-channel architecture to a multi-channel time-interleaved architecture, adding the dimension of parallel processing. This dimensional change enables the system to achieve high-speed conversion with reduced per-channel capacitance by distributing the conversion load across multiple channels
2Speed
If flash converter architecture is used to achieve high-speed conversion, then sampling frequency increases, but power consumption becomes 10 times larger
Solution Approach 1:
The flash converter architecture is segmented into multiple parallel channels, each performing a subset of the total comparisons. This segmentation reduces the number of comparisons each channel must perform simultaneously, thereby reducing power consumption while maintaining high overall conversion speed
Solution Approach 2:
Each channel performs a partial set of comparisons rather than all comparisons in parallel. This partial action approach reduces the instantaneous power requirement of each channel while the combined output of all channels achieves the desired high-speed conversion performance
3Speed
If pipelined ADC with non-linear scale is used to achieve high-speed conversion, then sampling frequency increases, but calibration complexity increases
Solution Approach 1:
The patent employs programmable gain amplifiers and variable thresholds that can be dynamically adjusted through calibration. This parameter change capability allows the system to adapt to non-linear scales while maintaining manageable calibration complexity through systematic adjustment of gain and threshold parameters
Data Source
AI summary
The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.