Tri-Level DAC Dual-Switch Layout for Data-Independent ISI Control
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Solution Overview
Problem
Current digital to analog converters (DACs) face challenges in mitigating intersymbol interference (ISI) due to unequal rise and fall times in current delivery, which worsens with increased operating frequencies and is not effectively addressed by existing techniques such as delayed driving, return to zero, and return to hold methods.
Innovation Solution
A duel-switch scheme is implemented for tri-level unit elements, where complementary switches are used in parallel to provide a baseline of switching activity, and the activation of switches is changed even in consecutive clock cycles to reduce data dependence and mitigate ISI, regardless of the digital input signal content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switching schemes are used in tri-level unit elements, then the DAC can operate at basic frequencies, but intersymbol interference (ISI) increases due to unequal rise and fall times in current delivery
Solution Approach 1:
The patent implements a periodic switching scheme where switches are activated in a systematic pattern across clock cycles. The controller activates switches based on a predetermined pattern that ensures periodic switching activity regardless of data content, which equalizes rise and fall times and mitigates ISI while enabling higher frequency operation
Solution Approach 2:
The patent changes the switching parameters by activating different sets of switches in different clock cycles according to a periodic pattern. This parameter change approach ensures that current delivery characteristics are equalized over time, reducing ISI and allowing the DAC to operate at higher frequencies without signal degradation
2Reliability
If switching activity is increased to mitigate ISI, then signal accuracy improves, but power consumption and silicon area increase
Solution Approach 1:
The patent divides the switching activity into segments across multiple switches (first set and second set of switches) that are activated in different clock cycles. This segmentation allows the system to achieve ISI mitigation through distributed switching rather than simultaneous full switching, reducing peak power consumption while maintaining signal accuracy
Solution Approach 2:
The periodic switching pattern ensures that not all switches are activated simultaneously in every clock cycle. Instead, switching activity is distributed periodically across clock cycles, which reduces instantaneous power consumption while still achieving the necessary ISI mitigation through consistent switching activity over time
Data Source
AI summary
Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.