Single-Slope ADC Latch Circuit With Minimal Switching Noise

Solution Overview

Problem

Existing latch circuits in single-slope ADCs consume significant power and generate noise due to frequent switching, leading to crosstalk and linearity issues in column-parallel digitization applications.

Innovation Solution

A minimal power latch circuit comprising a pair of set-reset latches operating according to specific equations, consuming power only at the moment of data capture and minimizing switching, thereby reducing power consumption and noise generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transparent latch or flip-flop clocked by comparator output is used, then data capture function is achieved, but power consumption increases and noise is generated due to frequent switching

Engineering Contradiction:

Improvedata capture functionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The latch circuit is designed to switch only periodically at the moment of data capture when the comparator trips, rather than switching continuously with every code change. The circuit uses the comparator output transition as a trigger to enable the latch momentarily, allowing data capture only at this specific periodic moment, thereby minimizing switching activity and power consumption.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The latch circuit dynamically changes its state based on the comparator output. The circuit transitions from a high-impedance or disabled state to an active state only when the comparator trips, allowing the latch to be dynamic rather than continuously active. This dynamic operation reduces power consumption by minimizing the time the latch spends in switching states.

Inventive Principle:

Principle #15Dynamics

2Reliability

If transparent latch or flip-flop clocked by comparator output is used, then data capture function is achieved, but noise and crosstalk increase due to frequent switching

Engineering Contradiction:

Improvedata capture functionVSAvoidnoise and crosstalk

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The latch circuit is designed to switch only periodically at the moment of data capture when the comparator trips, rather than switching continuously with every code change. The circuit uses the comparator output transition as a trigger to enable the latch momentarily, allowing data capture only at this specific periodic moment, thereby minimizing switching activity and power consumption.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The latch circuit dynamically changes its state based on the comparator output. The circuit transitions from a high-impedance or disabled state to an active state only when the comparator trips, allowing the latch to be dynamic rather than continuously active. This dynamic operation reduces power consumption by minimizing the time the latch spends in switching states.

Inventive Principle:

Principle #15Dynamics

3Loss of information

If latch switches every time code changes, then data is continuously updated, but power consumption becomes comparable to comparator current

Engineering Contradiction:

Improvedata update continuityVSAvoidpower consumption

Core Design Contradiction:

Loss of informationVSUse of energy by moving object

Solution Approach 1:

The latch circuit is designed to switch only periodically at the moment of data capture when the comparator trips, rather than switching continuously with every code change. The circuit uses the comparator output transition as a trigger to enable the latch momentarily, allowing data capture only at this specific periodic moment, thereby minimizing switching activity and power consumption.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8928379B2Minimal power latch for single-slope ADCs

Publication Date: 2015.01.06 CALIFORNIA INST OF TECH

AI summary

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.