Folding ADC Anti-Aliasing Structure With Fewer Differential Cells
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Solution Overview
Problem
High-resolution analog-to-digital converters using folding differential amplifier structures require a large number of additional differential and load circuits, leading to high current consumption and bulk, as well as reduced operating speed due to the complexity of the folding structure.
Innovation Solution
The proposed analog-digital converter reduces the number of additional differential and load circuits by using a configuration with N+1 differential circuits and N+2 load circuits per block, where additional differential and load circuits are connected differently to minimize their contribution to the output, while maintaining regularity of folding curves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of additional differential and load circuits are used in folding structures, then high-resolution conversion is achieved, but current consumption and device bulk increase significantly
Solution Approach 1:
The patent extracts and eliminates redundant differential circuits and load circuits from the folding structure. By carefully analyzing which circuits are truly necessary for maintaining folding curve regularity and which are excessive, the invention removes unnecessary components while preserving the essential conversion function and resolution accuracy.
Solution Approach 2:
The patent applies partial action by providing additional differential and load circuits only where strictly necessary to maintain folding curve regularity at critical points (beginning and end of conversion range), rather than uniformly across all circuits. This selective approach ensures sufficient precision without the excessive circuit count that would result from uniform redundancy.
2Measurement precision
If a large number of additional differential and load circuits are used in folding structures, then high-resolution conversion is achieved, but operating speed decreases due to structural complexity
Solution Approach 1:
By removing redundant circuits from the folding structure, the patent reduces the total number of switching elements and interconnections that must operate during conversion. This extraction of unnecessary components directly decreases the overall circuit complexity and reduces the time required for signal propagation and settling, thereby improving operating speed while maintaining the resolution achieved with the essential circuits.
3Quantity of substance
If the number of differential and load circuits is reduced, then current consumption and bulk are decreased, but integral non-linearity error increases
Solution Approach 1:
The patent applies local quality by concentrating additional differential and load circuits only at specific locations where they are most needed - at the beginning and end of the conversion range where folding curve regularity is most critical. Rather than uniformly distributing redundancy across all circuits, this localized approach maintains integral non-linearity error performance while minimizing the total number of circuits required.
Solution Approach 2:
The additional differential circuits and load circuits act as intermediary elements that compensate for the reduced number of standard circuits. These intermediary components are strategically positioned to maintain the regularity of folding curves and ensure accurate voltage comparison points, thereby preserving integral non-linearity error performance despite the overall reduction in circuit count.
Data Source
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AI summary
The invention relates to high-resolution analogue-digital converters using differential amplifier structures that are called anti-aliasing differential amplifiers made up of differential circuits (crossed differential pairs) and loads (cascode transistors). The anti-aliasing structure according to the invention comprises, when it is desired to make four curves folded over two periods within the useful range of voltages to be converted, four anti-aliasing blocks (one per curve). The first block comprises seven differential circuits (CR0 to CR6) and eight loads (CH0 to CH7), the outermost loads (CH0 and CH7) not being connected to the output of the block. The other blocks comprise six differential circuits (CR1 to CR6) and eight loads (CH0 to CH7), the final load (CH7) of each block not being connected to the output of this block. Compared with the existing structures, a smaller footprint, a lower consumption and a higher operating speed are achieved.