Switched-Capacitance ADC Converter for Lower-Power Bit Decisions
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face high power consumption due to large capacitors used in initial stages, which increases voltage and current flow, leading to reduced sensitivity to noise and error sources, and higher power usage.
Innovation Solution
Implementing a switched-capacitance digital-to-analog converter (SC-DAC) with two parallel groups of capacitors, where smaller capacitors are used for initial bits and larger capacitors for later bits, allowing the smaller capacitors to float during initial measurements, reducing power draw and increasing sensitivity to noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large capacitors are used in initial stages of ADC, then voltage and current flow increase, but power consumption increases and sensitivity to noise decreases
Solution Approach 1:
The patent applies dynamics by transitioning from static capacitance to switched capacitance architecture. The capacitor array is dynamically reconfigured during the conversion process, with capacitors being switched between different states (connected to input signal, ground, or reference voltage) based on the binary search algorithm progression. This dynamic switching allows the system to use smaller effective capacitance values during initial coarse measurements, reducing power consumption while maintaining measurement capability.
Solution Approach 2:
The patent segments the capacitance function into multiple smaller capacitor units that can be independently controlled and switched. Instead of using one large capacitor for all measurement stages, the total capacitance is divided into numerous smaller capacitors (e.g., 2^N capacitors for N-bit resolution) that are activated selectively during different phases of the conversion process. This segmentation enables the system to use only the necessary capacitance for each measurement stage, significantly reducing overall power consumption.
2Measurement precision
If large capacitors are used in initial stages of ADC, then voltage and current flow increase, but device complexity increases due to switching mechanisms
Solution Approach 1:
The patent implements universality through the use of a single capacitor array that serves multiple functions throughout the conversion process. The same set of switched capacitors is used for both the binary search algorithm and the final digital output generation. The capacitor array is reconfigured at different stages to perform coarse measurement, fine measurement, and voltage reconstruction, eliminating the need for separate capacitor sets for each function and thereby reducing overall device complexity.
Solution Approach 2:
The switched capacitor array serves itself by being reconfigured through the same control logic that drives the binary search algorithm. The digital-to-analog converter (DAC) portion of the switched capacitor array automatically generates the appropriate reference voltages needed for comparison during the binary search, eliminating the need for external voltage sources or additional control circuitry for each measurement stage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction in power consumption, potentially achieving a 60% reduction in power usage compared to static capacitance systems, while maintaining sensitivity to noise and error sources.
Implementation Method 1
A switched-capacitance digital-to-analog converter (SC-DAC) with two parallel groups of capacitors
Data Source
AI summary
A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit.