Hybrid Current-Switching DAC for Low Memory Effect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional digital to analog converters (DACs) experience memory effects and distortion at high frequencies, leading to non-linear analog output, and existing solutions either increase die size or consume excessive power, making them costly and inefficient for high-frequency applications.
Innovation Solution
A digital to analog converter design utilizing hybrid switched current cells, comprising a source switched series circuit and a drain switched series circuit coupled in parallel, which minimizes memory effects across process, temperature, and voltage variations, and maintains power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional current steering circuit cells are used to minimize charge injection, then memory effect is reduced, but power consumption increases significantly
Solution Approach 1:
The patent implements periodic action by using two-phase non-overlapping clock signals (PH1 and PH2) to alternately control the switching of current sources. During each phase, specific current sources are enabled while others are disabled, creating a periodic switching pattern that reduces charge injection into the bias voltage node compared to continuous steering operations.
Solution Approach 2:
The patent applies discarding and recovering by selectively disabling certain current sources during specific phases of operation. Current sources that would otherwise continuously steer current are instead discarded (disabled) during phases when their current is not needed, reducing overall power consumption while maintaining the ability to recover and enable them when required.
2Reliability
If capacitance is added to bias circuit output to minimize voltage spikes, then memory effect is reduced, but die size increases significantly
Solution Approach 1:
The patent extracts the problematic element (large capacitance) from the system and replaces it with an alternative mechanism. Instead of adding substantial capacitance to the bias circuit output to minimize voltage spikes, the invention uses controlled switching of current sources with complementary enable signals to achieve memory effect reduction without requiring large capacitive components.
Solution Approach 2:
The patent introduces intermediary elements in the form of switching circuitry controlled by phased clock signals. These switching circuits act as intermediaries between the current sources and the output, controlling charge injection patterns to reduce memory effect without requiring large capacitance values, thus avoiding increased die size.
3Use of energy by moving object
If simple switched current mirror approach is used, then power consumption is low, but memory effect and distortion increase at high frequencies
Solution Approach 1:
The patent applies dynamics by transitioning from a static simple switched current mirror to a dynamic multi-phase switching architecture. The system uses time-varying enable signals with different phases to control multiple current sources, creating dynamic charge injection patterns that cancel memory effects at high frequencies while maintaining power efficiency through selective activation of current sources.
Solution Approach 2:
The patent uses a composite architecture combining multiple current sources with different switching phases. Instead of relying on a single current mirror circuit, the invention composite together multiple current sources (first set and second set) that are switched in a coordinated manner, creating a system that achieves both low power consumption and reduced memory effect through the combined action of its components.
Data Source
AI summary
In one embodiment of the invention, a digital to analog convertor (DAC) is disclosed for converting a digital input signal into an analog output signal. The DAC includes a switch controller coupled to a digital input signal; a bias voltage generator coupled to a first terminal of an analog voltage power supply; and a switched current source array coupled to the switch controller and the bias voltage generator. The bias voltage generator generates a bias voltage. The switch controller generates a plurality of digital enable signals. The switched current source array includes a plurality of hybrid switched current cells coupled to the switch controller and the bias voltage generator. The plurality of hybrid switched current cells are coupled together at an analog output terminal to sum unit currents together, if any, and form the analog output signal in response to the digital input signal.