Interleaved Pipelined Binary-Search ADC for Low-Capacitance Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing low-resolution, high-speed analog-to-digital converters face challenges with high power consumption and large input capacitance, particularly in applications requiring sampling rates above a few hundred megasamples per second, where traditional architectures like time-interleaved SAR and flash converters are inefficient due to power requirements and capacitance issues.
Innovation Solution
A pipelined analog-to-digital converter with a hierarchical tree structure and tunable thresholds, utilizing variable capacitors for calibration and non-linear multiplying digital-to-analog converters, implements a binary search algorithm to reduce power consumption by minimizing the number of active comparators and compensating for non-linear distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved SAR architecture is used to achieve high sampling frequency, then sampling rate is improved, but input capacitance increases 10-20 times
Solution Approach 1:
The converter is divided into multiple stages, each performing a portion of the conversion process. The first stage performs coarse quantization and the second stage performs fine quantization, allowing high sampling rates to be achieved without proportionally increasing input capacitance.
Solution Approach 2:
The invention transitions from a single-dimensional time-interleaved approach to a two-dimensional staged approach, where the first stage handles coarse quantization and the second stage handles fine quantization, effectively reducing the input capacitance requirement while maintaining high sampling rates.
2Productivity
If flash converter architecture is used to achieve high conversion speed, then conversion rate is improved, but power consumption increases 10 times
Solution Approach 1:
The conversion process is segmented into two stages: a first stage performing coarse quantization with fewer comparators, and a second stage performing fine quantization. This segmentation reduces the total number of comparators needed compared to a full flash converter, thereby reducing power consumption while maintaining high conversion rates.
Solution Approach 2:
The first stage performs partial quantization (coarse quantization) and the second stage completes the conversion (fine quantization). This partial action approach allows the system to achieve high conversion rates without requiring all comparators to operate at full power simultaneously, thus reducing overall power consumption.
3Speed
If pipelined ADC with non-linear scale is used to achieve high frequency operation, then sampling frequency is improved, but non-linear distortion is introduced
Solution Approach 1:
The conversion process is divided into two stages: the first stage performs coarse quantization with a non-linear scale to achieve high sampling frequency, and the second stage performs fine quantization to correct the non-linear distortion introduced by the first stage, thereby maintaining measurement precision.
Solution Approach 2:
The first stage acts as an intermediary that performs coarse quantization with non-linear scaling, and the second stage serves as a mediator that corrects the non-linear distortion, allowing the system to achieve high sampling frequencies while maintaining measurement accuracy.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising - a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and - a plurality of amplifying circuits, - wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and - wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.