Asynchronous Data Stream Coalescing via Segmented FIFO Arbitration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional multiple-clock domain communication systems require large FIFO resources and extensive interconnects to manage asynchronous data streams, leading to inefficient use of resources and potential impracticality due to performance and routing constraints.

Innovation Solution

The system employs a plurality of synchronization FIFOs with a minimum number of entries to synchronize and buffer data, coupled with an arbitration circuit that reads data from these FIFOs in response to a local clock signal, reducing the need for extensive buffering and interconnects by using a single buffer FIFO for downstream processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional FIFOs with large number of entries are used to buffer asynchronous data streams, then data synchronization and buffering capacity are improved, but device complexity and resource consumption increase

Engineering Contradiction:
Improvedata synchronizationVSAvoidFIFO resource consumption
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the buffering function by using multiple small FIFOs (one per input data stream) instead of a single large FIFO. Each FIFO is sized to handle only the synchronization requirements for its specific data stream, reducing the overall resource consumption while maintaining effective data synchronization across multiple asynchronous streams.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges the output of multiple small FIFOs through a shared read port that consolidates data from all FIFOs into a single output data stream. This combining approach allows the system to achieve the buffering capacity of a large FIFO while using the resource efficiency of multiple small FIFOs, resolving the contradiction between synchronization capability and resource consumption.

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If multiple FIFOs with large entry capacity are used to buffer incoming data streams, then buffering capacity during transient periods is improved, but the number of interconnects and routing complexity increase

Engineering Contradiction:
Improvebuffering capacityVSAvoidinterconnect complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent uses a shared read port that merges data from multiple FIFOs into a single output data stream. This single output bus replaces what would otherwise require multiple separate interconnects, significantly reducing routing complexity while maintaining the buffering capacity provided by the multiple FIFOs. The shared read port acts as a consolidation point that simplifies the interconnect structure.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If flow control circuitry limits average throughput of incoming data streams, then receiving agent throughput constraints are satisfied, but transient throughput peaks still cause buffering requirements

Engineering Contradiction:
Improveaverage throughput controlVSAvoidbuffering entries required
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments the buffering requirement by using multiple small FIFOs, each sized to handle only the transient buffering needs for its specific data stream. Since flow control limits the average throughput of each stream individually, the buffering capacity required for each FIFO is reduced, allowing the system to satisfy throughput constraints while minimizing total buffering entries.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3776176B1System and method for asynchronous, multiple clock domain data streams coalescing and resynchronization
Publication Date: 2023.11.08 DEGIRUM CORP
  • EP3776176B1 patent drawingFigure 1
  • EP3776176B1 patent drawingFigure 2A
  • EP3776176B1 patent drawingFigure 2B

AI summary

A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (SMIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. SMIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.