Digital Storage TRIZ Cases

Partitioned memory arrays in a dual-port DRAM enable simultaneous data transfer, eliminating single-port bottlenecks in image processing systems.

A sensing circuit uses two reference magneto tunnel junctions to read data states.

A calibration circuit adjusts resistance values across pull-up units to ensure impedance matching for semiconductor input output pads.

Bit-line drive auxiliary circuit adjusts potentials on parallel bit lines to ensure accurate voltage application across memory cell intersections.

Distinct metal interconnections between magnetic tunnel junctions enhance electrical connection reliability.

A redundant memory device circuit structure simulates read operations to determine critical word line voltage levels.

Segmented reference cells expand the sensing margin against process variations, enabling faster read access speeds for MRAM devices.

A charge sharing circuit accelerates reference voltage settling in ferroelectric memory cells.

A semiconductor device uses a burst end signal generation circuit to produce write and read burst end signals based on latched burst modes.

A distributed targeted refresh system schedules auto-refresh and targeted operations to average power draw across memory cycles.

A period signal generation circuit uses temperature-dependent voltage selection to control internal node discharge and determine periodic signal cycle time.

A semiconductor memory device reduces test data writing time through simultaneous word line activation and direct data latching.

Merging level shifters and latches reduces circuit area and performance delays in memory devices during power domain transitions.

CAM search logic computes checksums to detect errors, reducing hardware overhead in small area memory macros.

A latchless memory system uses a central timing controller to coordinate read and write operations across the array.

Segmented driving units connected to different main word lines eliminate parasitic coupling capacitance between closely spaced signal lines.

Segmented MTJ devices with parallel resistive dividers prevent read disturb errors while reference bitcells ensure accurate ternary state detection.

A power management circuit controls internal voltage ramp-up timing using clamp and pump circuits.

A test circuit routes data through global I/O lines to simplify semiconductor memory structures.

Segmented voltage pulses with sensing feedback narrow MLC resistance margins, reducing read errors while maintaining high memory density.

A complementary magnetic memory cell uses spin orbit torque to write data via a unidirectional current path.

An integrated write driver circuit merges multiplexor selection with data writing to generate strong driver signals.

A ferroelectric memory bit-cell uses vertically stacked capacitors to increase storage density.

Segmenting synapse weights into unit weighting elements resolves binary storage limits and improves integration density.

A configurable input buffer uses a de-emphasis circuit to adjust signal gain across varying frequencies.

Segmented subarrays use shared ground wires to fix nonselected line potentials, reducing parasitic capacitance and preventing data disturbance.

A dynamically replicated memory system pairs compatible faulty pages to reuse otherwise unusable failed memory space.

Segmented power switching maintains read noise margin while reducing energy consumption during write and standby modes.

Virtual power supply nodes isolate peripheral circuits from main rails, cutting standby leakage while preventing read disturb during active cycles.

A detection circuit identifies gapless pattern sections in read signals to trigger compensating operations within the internal circuit.

A synchronization circuit segments data streams into multiple small FIFOs and arbitrates reads using a local clock signal to consolidate outputs.

A pseudo-triple-port SRAM bitcell uses two word lines and a single access transistor pair to enable independent read and write operations.

Introducing random telegraph noise via memristor crossbars helps Hopfield networks escape local minima and reach global solutions.

Titanium nitride barriers prevent cobalt titanium silicide overgrowth into the substrate, reducing leakage current and contact resistance.

A self-referencing read method compares bit line voltage with a delayed reference to detect phase change states.

Segmented test patterns and dummy operations simulate actual environments, improving reliability without increasing equipment complexity.

A data transceiver system uses delay units and an error detector to adjust signal timing for precise synchronization.

Pattern cell groups enable forward-looking voltage selection, reducing read latency and improving accuracy despite resistance drift.

Under-the-array circuit components perform neural network operations directly on the NVM die to reduce data transfer time and power consumption.

A semiconductor memory sense amplifier uses a negative supply voltage to determine the low level of amplified data.

Detecting resistance changes during programming signals determines data states, reducing errors and speeding operations.

Memory controller counts reference signal transitions to adjust input buffer bias levels in real-time.

Multi-function access transistors merge read and write roles in a dual-read SRAM cell, resolving the trade-off between die area and write capability.

A column multiplexer uses single-ended bit lines and pre-charging to generate data read outputs from memory arrays.

A nonvolatile resistance change device uses segmented variable resistance layers to control conductive filament growth rates for stepwise resistance changes.

A semiconductor memory system manages bank active periods using signal detection units to identify activated word lines.

Single crystal epitaxial electrodes reduce coercive fields in hexagonal ferroelectric devices by minimizing negative impacts from supporting structures.

Dynamic write driver circuit balances current symmetry for MRAM writes by adjusting source voltages, preventing tunneling layer damage from excessive current.

A voltage level shifting circuit translates write signals between domains to enable reliable SRAM operations.