Dual-Read SRAM Cell Using Multi-Function Access Transistors
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Solution Overview
Problem
Existing SRAM memory cells face challenges in achieving dual-read functionality while maintaining write capability and minimizing power consumption and die area, with five-transistor (5T) cells sacrificing write capability and six-transistor (6T) cells requiring more access transistors for dual-read operations.
Innovation Solution
A dual-read SRAM memory structure is proposed, utilizing two bit lines where only one is used for single-read operations, with the other bit line serving as a reference, allowing dual-read functionality without increasing the number of access transistors, thus maintaining write performance similar to 6T cells while reducing die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 5T memory cell structure is used to reduce die area, then die area is reduced, but write capability is sacrificed
Solution Approach 1:
The access transistor is designed to perform multiple functions: serving as both a read access transistor and a write driver transistor. This multi-functional design allows the memory cell to achieve dual-read capability and maintain write capability simultaneously without requiring separate dedicated transistors for each function, thus reducing die area while preserving write capability.
2Reliability
If 6T memory cell structure is used to maintain write capability, then write capability is maintained, but more access transistors are required for dual-read operations increasing die area
Solution Approach 1:
The access transistor is designed to perform multiple functions: serving as both a read access transistor and a write driver transistor. This multi-functional design allows the memory cell to achieve dual-read capability and maintain write capability simultaneously without requiring separate dedicated transistors for each function, thus reducing die area while preserving write capability.
3Adaptability or versatility
If multiple access transistors are added to achieve dual-read functionality, then dual-read capability is improved, but device complexity and die area increase
Solution Approach 1:
The access transistor is designed to perform multiple functions: serving as both a read access transistor and a write driver transistor. This multi-functional design allows the memory cell to achieve dual-read capability and maintain write capability simultaneously without requiring separate dedicated transistors for each function, thus reducing die area while preserving write capability.
Solution Approach 2:
The patent merges the read access function and write driver function into a single access transistor. By combining these functions that were previously performed by separate transistors in conventional designs, the overall device complexity is reduced while achieving the desired dual-read capability.
4Speed
If dual-read functionality is implemented with conventional structures, then read speed is improved, but power consumption increases
Solution Approach 1:
The access transistor serves dual purposes as both read access and write driver, eliminating the need for separate dedicated write driver transistors. This self-service design reduces the total number of active transistors in the memory array, thereby reducing overall power consumption while maintaining fast read and write operations.
Data Source
AI summary
A memory array includes a first memory cell and a second memory cell, each including a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory device also includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell and a fourth bit line coupled to the second access transistor of the second memory cell.