Charge Sharing Circuit for Ferroelectric Memory Settling Time
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Solution Overview
Problem
Ferroelectric memory cells face slow data reading speeds due to long settling times caused by small FRAM cell currents and low slew rates, which hinder high-speed data access and integration density.
Innovation Solution
A charge sharing circuit is implemented to provide electrical charges to the gate terminals of transistors, reducing the settling time of reference voltages and improving data reading speed, while calibration methods adjust parameters to compensate for component mismatches and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional ferroelectric memory reading method is used, then data reading can be performed, but settling time is long due to small FRAM cell currents and low slew rates
Solution Approach 1:
A charge sharing circuit is introduced as an intermediary component between the memory cells and the sensing circuitry. This circuit includes a capacitor that shares charge with the gate terminals of transistors, providing additional current to accelerate the settling process without altering the fundamental memory cell structure or operation
Solution Approach 2:
The invention changes the electrical parameters of the reading circuit by introducing a programmable electrical source that can provide variable amounts of charge to the capacitor. By adjusting the charge amount, the slew rate of the reference voltage is improved, thereby reducing settling time and enhancing data reading speed
2Quantity of substance
If higher integration density is achieved, then more memory cells can be packed, but component mismatches increase affecting performance
Solution Approach 1:
A calibration circuit is implemented that provides feedback to detect and compensate for component mismatches. The calibration circuit measures actual component values and adjusts operating parameters to compensate for variations, ensuring consistent performance across densely packed memory cells with varying tolerances
Solution Approach 2:
The invention introduces dynamic adjustment capabilities through programmable electrical sources and switches that can be configured during calibration and operation. This allows the system to adapt to manufacturing variations by dynamically adjusting charge sharing parameters, maintaining performance consistency despite increased integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces settling time, enhancing data reading speed and accuracy, and improves the integration density of ferroelectric memory cells, addressing the limitations of traditional ferroelectric memory technologies.
Implementation Method 1
a capacitor coupled to the first switch, and a second switch coupled to the capacitor, the first switch, and the plurality of gate terminals of the plurality of transistors. The programmable electrical source is configured to provide electrical charges to the capacitor when the first switch is turned on and the second switch is turned off. The capacitor is configured to provide at least a portion of the electrical charges to the plurality of gate terminals of the plurality of transistors when the first switch is turned off and the second switch is turned on.
Data Source
AI summary
Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, first data from a plurality of memory cells is sensed, each of the first data corresponding to a first bit. Measurements of first currents converted from voltages of the first data are obtained. Second data from the plurality of memory cells is sensed, each of the second data corresponding to a second bit which is different from the first bit. Measurements of second currents converted from voltages of the second data are obtained. One or more parameters corresponding to one or more components of a charge sharing circuit are adjusted until each of a plurality of reference currents provided by a plurality of transistors is within a predetermined range of a nominal value determined based on the measurements of first currents and the measurements of second currents.