Dynamic MRAM Write Driver Voltage Symmetry

Solution Overview

Problem

Existing magnetic random access memory (MRAM) technologies face an asymmetry in current levels during write '0' and write '1' operations, leading to insufficient current for writing '1' or excessive current for writing '0', which can damage the tunneling layer due to the asymmetry in gate-to-source and drain-to-source voltages required for state transitions.

Innovation Solution

A write driver circuit that independently controls the voltages applied to the terminals of MRAM cells to achieve symmetry in current levels during write operations by varying the voltages applied to the source and drain terminals of the select transistor, allowing for precise control of current flow during both '0' and '1' writes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the write driver circuit is designed to deliver sufficient current for writing '0' (using NMOS transistor with higher current drive), then the current level for write '0' is adequate, but the current level for write '1' becomes excessive and may damage the tunneling layer

Engineering Contradiction:

Improvewrite '0' operation reliabilityVSAvoidexcessive current damage to tunneling layer

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the operating parameters of the NMOS transistor by dynamically adjusting its source voltage level. For write '0' operations, the source voltage is maintained at ground potential to enable high current drive. For write '1' operations, the source voltage is raised to a positive level (e.g., 0.5V to 1.0V), which reduces the effective voltage difference across the transistor and thereby limits the current to a safe level that prevents tunneling layer damage while still achieving the required state transition

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the write driver circuit is designed to deliver sufficient current for writing '1' (increasing current drive capability), then the current level for write '1' is adequate, but the current level for writing '0' becomes excessive and may damage the tunneling layer

Engineering Contradiction:

Improvewrite '1' operation reliabilityVSAvoidexcessive current damage to tunneling layer

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the operating parameters of the NMOS transistor by dynamically adjusting its source voltage level. For write '0' operations, the source voltage is maintained at ground potential to enable high current drive. For write '1' operations, the source voltage is raised to a positive level (e.g., 0.5V to 1.0V), which reduces the effective voltage difference across the transistor and thereby limits the current to a safe level that prevents tunneling layer damage while still achieving the required state transition

Inventive Principle:

Principle #35Parameter changes

3Area of stationary object

If asymmetric voltage levels are used for write '0' and write '1' operations due to NMOS transistor characteristics, then the circuit area is minimized, but the current asymmetry causes unreliable state transitions

Engineering Contradiction:

Improvetransistor areaVSAvoidstate transition reliability

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the operating parameters of the NMOS transistor by dynamically adjusting its source voltage level. For write '0' operations, the source voltage is maintained at ground potential to enable high current drive. For write '1' operations, the source voltage is raised to a positive level (e.g., 0.5V to 1.0V), which reduces the effective voltage difference across the transistor and thereby limits the current to a safe level that prevents tunneling layer damage while still achieving the required state transition

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution ensures balanced current levels for both write operations, preventing damage to the tunneling layer and enhancing the reliability of MRAM cell state transitions, with improved current symmetry resulting in enhanced operational stability and reduced risk of layer damage.

Implementation Method 1

the voltage potential of reference layer 12 is increased relative to that of free layer 16. This voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16 to the anti-parallel state

Methodology Applied

Scientific EffectSpin torque transfer:

Implementation Method 2

This voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum

Methodology Applied

Scientific EffectTunneling:

Data Source

PatentUS8077508B1Dynamic multistate memory write driver

Publication Date: 2011.12.13 SAMSUNG SEMICONDUCTOR INC

AI summary

A circuit includes, in part, a multitude of magnetic random access memory cells, one or more column decoders, one or more row decoders, and a write driver circuit. The write driver circuit is responsive to data signal as well as to read/write signals. During writing of a first data to a selected magnetic random access memory cell, the write driver circuit causes the first signal line to be at a second voltage and the second signal line to be at the first voltage. The second voltage is greater than the first voltage. During writing of a second data to the selected magnetic random access memory cell, the write driver circuit cause the first signal line to be at a third voltage and the second signal line to be at the second voltage. The third voltage is smaller than the first voltage.