Dual-Port DRAM Architecture for Simultaneous Data Transfer
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Solution Overview
Problem
Conventional display systems face bottlenecks in image data movement due to single-port DRAM design, which incurs size and power penalties, limiting their efficiency in high-definition and high-frame-rate applications.
Innovation Solution
A dual-port dynamic random access memory (DRAM) architecture with separate input and output ports and partitioned memory arrays allows simultaneous reading and writing, utilizing buffers and control logic to manage data movement efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-port DRAM is used, then device complexity is reduced, but productivity deteriorates due to time-multiplexed data movement
Solution Approach 1:
The memory system is segmented into multiple independent ports (first port and second port), each capable of simultaneous data movement operations. This segmentation allows parallel access to the memory array, eliminating the time-multiplexing bottleneck of single-port designs while maintaining manageable complexity through modular port structures.
Solution Approach 2:
The patent transitions from temporal multiplexing (single port alternating between read/write in time) to spatial parallelism (multiple ports operating simultaneously). By adding the dimension of multiple concurrent access paths, the system achieves higher productivity without proportionally increasing complexity, as each port follows a standardized interface design.
2Productivity
If dual or multi-port memory is implemented, then productivity improves through simultaneous read/write, but device complexity increases
Solution Approach 1:
The buffer structure is designed with multi-functionality to serve multiple ports simultaneously. The same buffer resources can be dynamically allocated to different ports based on operational needs, allowing the system to achieve simultaneous read/write operations without requiring completely separate buffer structures for each port, thereby controlling complexity.
Solution Approach 2:
The patent introduces buffer structures as intermediary elements between the multiple ports and the memory array. These buffers act as mediators that manage data flow, temporary storage, and coordination between concurrent operations, simplifying the control logic required to manage multi-port operations while maintaining high productivity.
3Productivity
If conventional multi-port design is used, then data movement efficiency improves, but size penalty increases
Solution Approach 1:
The patent merges shared resources (memory array, control logic, and buffer structures) among multiple ports to reduce overall size. Instead of providing dedicated separate structures for each port, the design combines common elements that can be shared across ports, achieving high data movement efficiency for image data while minimizing the area penalty through resource consolidation.
Data Source
AI summary
Multiport memory architecture is disclosed herein. An example memory includes an input port, a memory array, and an output port. The input port is coupled to receive data blocks and includes first and second buffers coupled to temporarily store alternate data blocks, and the output port is coupled to provide data blocks from the memory array. The memory array is partitioned into first and second partitions, with the first partition coupled to receive data blocks from the first buffer and the second partition coupled to receive data blocks from the second buffer, and the input port and the memory array are coupled to receive control signals to simultaneously receive a first data block at the first buffer, transfer a second data block from the second buffer to a first address in the second partition, and provide a third data block stored at a third address of the first partition.