Integrated Level Shifter Latch Circuit Area Reduction
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Solution Overview
Problem
Conventional memory devices experience performance delays and increased circuit area due to the use of series latch circuits and level shifter circuits for shifting signals between different power supply domains.
Innovation Solution
The integration of level shifter and latch circuitry within the memory device, which performs both level shifting and latching functions, allowing signals to be transitioned between power supply domains while maintaining data integrity during power-down modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If series latch circuits and level shifter circuits are used to shift signals between different power supply domains, then signal transition between power domains is achieved, but circuit area increases and performance delays occur
Solution Approach 1:
The patent combines the level shifter circuit and latch circuit into a single integrated circuit block. The level shifter portion transitions signals between first and second power supply domains, while the latch portion captures and holds the signal value. This merging eliminates the need for separate series-connected latch and level shifter circuits, thereby reducing overall circuit area while maintaining signal transition reliability between power domains.
Solution Approach 2:
The integrated level shifter and latch circuit serves multiple functions within a single circuit block: it performs level shifting between different power supply domains, latches signal values for timing synchronization, and provides isolation during power-down modes. This multi-functionality replaces what previously required separate dedicated circuits, reducing total circuit area while maintaining all necessary signal processing capabilities.
2Reliability
If series latch circuits and level shifter circuits are used to shift signals between different power supply domains, then signal transition between power domains is achieved, but performance delays increase
Solution Approach 1:
By merging the level shifter and latch circuits into a single integrated block, the patent eliminates the sequential processing delays inherent in series-connected circuits. The combined circuit can perform level shifting and latching operations simultaneously or in a more tightly synchronized manner, reducing the overall time required for signal transition between power domains while maintaining reliability.
3Reliability
If separate level shifter and latch circuits are used, then signal level shifting is achieved, but device complexity increases
Solution Approach 1:
The patent integrates the level shifter circuit and latch circuit into a single circuit block with shared circuit elements and control logic. This merging reduces the number of discrete components, interconnections, and control signals required, thereby simplifying the overall device architecture while maintaining the essential signal level shifting capability between different power supply domains.
Data Source
AI summary
A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.