Column Multiplexer for SRAM Using Single-Ended Bit Lines
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Solution Overview
Problem
In smaller SRAM memory arrays, differential amplifiers become impractical due to their large size, and gate-type sense circuits limit the number of memory rows, while column multiplexers can reduce speed by applying an undesirable load on column bit lines.
Innovation Solution
A column multiplexer design that uses single-ended bit lines, pre-charging, and switching a control node between supply voltage rails based on bit line logic states to generate a data read output, reducing circuitry overhead and maintaining high-speed read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a differential amplifier is used for reading data from memory cells, then data reading capability is achieved, but circuit area becomes too large for smaller memory arrays
Solution Approach 1:
The patent extracts the essential sensing function from the full differential amplifier circuit and implements it using a minimal gate-type sense circuit. This sense circuit uses a single MOSFET switch and a sense amplifier that only needs to detect one bit line voltage level (high or low), rather than requiring the complex differential pair structure of a full differential amplifier. This extraction maintains data reading capability while dramatically reducing circuit area.
Solution Approach 2:
The patent employs a simple gate-type sense circuit that can be implemented with minimal circuit elements (essentially a single MOSFET switch and a simple amplifier), replacing the expensive and complex differential amplifier. This simplified circuit achieves the same functional purpose (reading data) with significantly reduced resource consumption, making it suitable for smaller memory arrays where area is constrained.
2Area of stationary object
If a gate-type sense circuit is used to reduce circuit area, then area efficiency is improved, but the number of memory rows is limited to 8-32
Solution Approach 1:
The patent segments the memory array into multiple banks, with each bank containing a gate-type sense circuit. This segmentation allows the memory array to be organized in a way that accommodates a larger total number of rows while maintaining the area efficiency of gate-type sense circuits. Each sense circuit handles a specific subset of rows (a bank), and multiple banks work together to service the entire memory array, effectively extending the usable row capacity beyond what a single sense circuit could handle.
Solution Approach 2:
The patent makes the gate-type sense circuit multi-functional by enabling it to serve multiple memory rows through the bank segmentation approach. A single gate-type sense circuit in a bank can service multiple rows within that bank, and multiple banks can service the entire array. This universal approach allows the same simple circuit structure to adapt to larger memory arrays with more rows by distributing the workload across multiple identical sense circuits in different banks.
3Reliability
If a column multiplexer is used to access data from memory cells, then data access capability is improved, but speed is reduced due to loading on column bit lines
Solution Approach 1:
The patent extracts the data latching function from the column multiplexer and implements it separately using a latch circuit. This separation allows the column multiplexer to focus solely on switching and data access functions without the added complexity and loading effects of integrated latching. The latch circuit independently captures and holds the data after it has been transferred from the memory cell, eliminating the need for the multiplexer to perform both switching and latching functions simultaneously. This extraction reduces the loading on column bit lines and improves read speed.
Solution Approach 2:
The patent segments the data readout process into distinct phases: data transfer from memory cell to multiplexer, data latching by the latch circuit, and data output. This segmentation allows each component to optimize its specific function without interfering with others. The column multiplexer handles only the transfer function with minimal loading, while the separate latch circuit handles the data capture function. This functional segmentation reduces the overall loading on column bit lines during the read operation, thereby improving read speed.
Data Source
AI summary
One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.