Low Power SRAM Voltage Control for Read Stability
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Solution Overview
Problem
Conventional 6T SRAMs face challenges in maintaining cell array supply voltage at a low level during Write mode to minimize power consumption while ensuring adequate Read Static Noise Margin (RSNM) and reducing power consumption in Read mode, as high cell array supply voltage is required for Read performance, leading to increased power usage and potential cell instability.
Innovation Solution
The SRAM design incorporates a power supplying circuit that keeps the cell array supply voltage low during Write mode and raises it only for selected columns during Read mode, utilizing a simple control circuit structure and power-switch devices to minimize power consumption and noise, achieving Ultra-Low-Power (ULP) and Absolutely-Lowest-Power (ALP) modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cell array supply voltage is raised to maintain adequate RSNM during Read operation, then Read performance is improved, but power consumption increases
Solution Approach 1:
The memory array is divided into multiple independently power-controlled segments or blocks. During Read operation, only the specific segment containing the accessed cell receives elevated supply voltage to maintain RSNM, while other segments remain at lower voltage to minimize power consumption.
Solution Approach 2:
The supply voltage is applied locally only to the specific column or segment being accessed during Read operation, rather than raising the voltage for the entire cell array. This localized voltage application maintains adequate RSNM for the accessed cell while keeping power consumption low in unaccessed areas.
2Use of energy by moving object
If the cell array supply voltage is kept low during Write operation to minimize power consumption, then power consumption is reduced, but writing data into the memory cell becomes difficult
Solution Approach 1:
The supply voltage to the memory cell is dynamically adjusted based on the operation mode. During Write operation, the voltage is temporarily boosted only for the duration of the write pulse to enable successful data writing, then quickly returned to low voltage level to minimize power consumption during the sustained Write mode.
Solution Approach 2:
The elevated supply voltage is applied in periodic bursts or pulses during Write operation rather than continuously. The voltage is raised only when data writing is actively occurring and then reduced to low level, creating a periodic voltage pattern that enables writing while minimizing overall power consumption.
3Reliability
If the cell array supply voltage is raised for the entire array during Read operation, then Read performance is maintained, but switching power and noise increase
Solution Approach 1:
The memory array is segmented into multiple independently power-controlled blocks. During Read operation, the supply voltage is raised only for the specific segment containing the accessed cell, while other segments remain at low voltage. This segmentation reduces the total capacitance that needs to be switched, thereby reducing switching power and noise.
Solution Approach 2:
The elevated supply voltage is applied locally only to the specific column or segment being accessed during Read operation. This localized voltage application minimizes the switching activity and associated power consumption and noise generation, while still maintaining adequate RSNM for the accessed cell.
Data Source
AI summary
A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.