Semiconductor Memory Voltage Drop Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, voltage drops across memory cells pose a significant challenge, particularly in high-density memory cells, leading to inaccurate operation voltages and limitations in reducing chip size and cost.
Innovation Solution
A semiconductor memory device with parallel word lines and bit lines, incorporating a drive circuit, sense amplifier circuit, and a bit-line drive auxiliary circuit to adjust potentials on the bit lines based on data read from the memory cells, ensuring voltage drop compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimension type memory cell structure is used to increase density, then memory element density is improved, but voltage drop in word line or bit line increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage levels applied to word lines and bit lines based on their respective resistance values. The control circuit modifies voltage parameters according to measured resistance changes, compensating for voltage drops in the three-dimension type memory cell structure to maintain reliable operation at high density.
Solution Approach 2:
The patent implements feedback by measuring the resistance of word lines and bit lines, comparing the measured resistance with reference resistance values, and adjusting the voltage applied to these lines accordingly. This closed-loop feedback mechanism compensates for voltage drops and ensures accurate data read/write operations in high-density memory cells.
2Manufacturing precision
If resistance of word line or bit line increases due to reduction in rule, then manufacturing precision is improved, but voltage drop increases causing inaccurate operation voltages
Solution Approach 1:
The patent changes voltage parameters dynamically based on measured resistance values of word lines and bit lines. By adjusting voltage levels according to actual resistance conditions, the system compensates for voltage drops caused by reduced pattern rules, maintaining accurate operation voltages despite manufacturing precision improvements.
Solution Approach 2:
The patent uses feedback mechanisms to measure resistance values of word lines and bit lines, compare them with reference values, and adjust voltage application accordingly. This feedback loop compensates for voltage drops resulting from tighter manufacturing rules, ensuring accurate operation voltages are maintained.
3Reliability
If voltage drop compensation is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a control circuit that performs multiple functions: measuring resistance of word lines and bit lines, comparing with reference values, determining voltage drop compensation values, and adjusting voltage application. This multi-functional approach consolidates complexity into a single control circuit rather than requiring separate compensation mechanisms for each line.
Solution Approach 2:
The patent implements self-service by having the control circuit automatically measure resistance, determine compensation values, and adjust voltages without external intervention. The system self-regulates voltage drops by continuously monitoring its own state and making corrections, reducing the need for external complexity while improving reliability.
Data Source
AI summary
A semiconductor memory device comprises a plurality of parallel word lines, a plurality of parallel bit lines formed crossing the plurality of word lines, and a plurality of memory cells arranged at intersections of the word lines and the bit lines. Each memory cell has one end connected to the word line and the other end connected to the bit line. The device also comprises a drive circuit operative to selectively apply a voltage for data read/write across the word line and the bit line. It further comprises a sense amplifier circuit connected to the plurality of bit lines and operative to read/write data stored in the memory cell. The device also comprises a bit-line drive auxiliary circuit operative to selectively adjust the potentials on the plurality of bit lines based on data read out of the memory cell by the sense amplifier circuit.