NVM Die Deep Learning Accelerator Integration
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Solution Overview
Problem
Current deep learning neural networks face challenges in achieving high-performance, efficient, and low-power processing due to the time-consuming nature of massive parallel computations required for feedforward and backpropagation operations in complex neural networks.
Innovation Solution
The implementation of deep learning accelerators within a non-volatile memory (NVM) die, utilizing under-the-array or next-to-the-array components to perform neural network operations and employing NAND-based on-chip copy and update functions to efficiently update synaptic weights without the need for external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If deep learning neural networks are implemented using external processing components, then computational capability is achieved, but data transfer time and power consumption increase
Solution Approach 1:
The patent merges the neural network processing component with the non-volatile memory die by forming the processing component using under-the-array or next-to-the-array components of the memory device. This integration eliminates the need for separate external processing components and reduces data transfer time between memory and processor by enabling processing to occur directly on the memory die.
2Productivity
If deep learning neural networks are implemented using external processing components, then computational capability is achieved, but power consumption increases
Solution Approach 1:
The patent merges the neural network processing component with the non-volatile memory die by forming the processing component using under-the-array or next-to-the-array components of the memory device. This integration eliminates the need for separate external processing components and reduces data transfer time between memory and processor by enabling processing to occur directly on the memory die.
3Adaptability or versatility
If synaptic weights are updated using traditional read-modify-write operations, then weight updates are achieved, but processing complexity and time increase
Solution Approach 1:
The patent implements an on-chip copy with update component that enables the memory device to perform synaptic weight updates autonomously without requiring external controller intervention. The component senses synaptic weights, performs neural network operations to modify weights, and executes NAND-based on-chip copy and update functions to save modified weights back to the memory array, allowing the memory device to serve itself for weight update operations.
Data Source
AI summary
Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.