MRAM Sensing Amplifier Reference Cell Segmentation
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Solution Overview
Problem
Conventional MRAM read schemes face limitations in sensing margin due to temperature and process-induced disparities in the Magneto-Resistance (MR) ratio of cells, leading to unreliable data detection and slower data read access, resulting in a performance gap between logic circuits and MRAM memory devices.
Innovation Solution
A sensing circuit and method utilizing high and low reference cells with predetermined resistance margins, coupled with differential amplifiers and a sense amplifier, to generate a digital output representing the resistance state of MRAM memory cells, thereby increasing the sense margin and improving read access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sense amplifier design with single reference current is used, then device complexity is reduced, but sensing margin decreases and reliability worsens due to temperature and process-induced disparities
Solution Approach 1:
The reference current generation is segmented into multiple reference currents (first reference current from high reference cell, second reference current from low reference cell) instead of using a single reference current. This segmentation allows differential comparison against both high and low resistance states, improving sensing reliability by accommodating process and temperature variations.
Solution Approach 2:
The invention changes the reference current parameters by generating multiple reference currents with different magnitude relationships to the memory cell currents. The first reference current has a first relationship (e.g., higher) and the second reference current has a second relationship (e.g., lower), creating expanded sensing margins that adapt to varying operating conditions.
2Speed
If conventional single-stage sensing is used, then device complexity is minimized, but read access speed is insufficient to match logic circuit frequencies
Solution Approach 1:
The sensing operation is divided into multiple stages: a first sense amplifier stage that performs initial differential comparison and a second sense amplifier stage that performs final determination. This multi-stage segmentation enables faster read access by breaking down the sensing operation into manageable steps that can be executed at higher frequencies.
Solution Approach 2:
The first sense amplifier stage performs preliminary sensing and comparison before the final decision is made by the second sense amplifier stage. This preliminary action prepares the signal in advance, allowing the final stage to operate faster and achieve overall high-speed performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and speed of MRAM data read operations by increasing the sensing margin, reducing the impact of cell variations, and enabling more accurate detection of resistance states, thus improving the performance of MRAM devices.
Implementation Method 1
sensing the resistance state of an MRAM memory cell... resistance of the high reference cell in high resistance state... resistance of the low reference cell in low resistance state
Data Source
AI summary
A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state. The resistance of the low reference cell in low resistance state has a second margin of difference from the resistance of the memory cell in low resistance state. Differential amplifiers coupled to the memory cell and the high and low reference cells provide a digital output representing the resistance state of the memory cell.


