Data Transceiver Error Correction via Dynamic Delay Adjustment
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Solution Overview
Problem
In data transceiver systems with separate I/O ports, errors in the data frame lock process are difficult to detect and correct due to the complexity of defining phase relations between signals, leading to potential operational failures.
Innovation Solution
A data transceiver system is designed with a data transmitter and receiver that include delay units, an error detector, and a delay controller. The system outputs reference clock signals and data signals, determines if a data frame is locked, and adjusts delay codes to correct errors by generating error signals and varying delay times, allowing for precise synchronization and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate I/O ports are used to increase mounting density and support high-speed operation, then productivity and speed are improved, but device complexity increases and error detection capability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the receiver detects phase relation errors between data signals and clock signals, generates error detection signals, and feeds them back to the transmitter. The transmitter then adjusts transmission timing based on this feedback, enabling automatic correction of phase synchronization issues that arise from using separate I/O ports.
2Adaptability or versatility
If separate I/O ports are used to increase mounting density, then device integration is improved, but error detection capability in data frame lock process deteriorates
Solution Approach 1:
The patent introduces an intermediary error detection mechanism that mediates between the separate I/O ports and the data frame lock process. The receiver monitors the locking status of data frames and generates intermediate error detection signals that indicate whether phase synchronization has been achieved, making the detection process explicit rather than implicit.
Solution Approach 2:
The patent replaces implicit mechanical synchronization assumptions with explicit electronic error detection and correction mechanisms. Instead of relying on physical phase alignment alone, the system uses electronic error detection signals and automated timing adjustments to ensure proper synchronization.
3Measurement precision
If multiple delay units are added to correct phase relations, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic delay adjustment where the amount of delay applied to data signals is not fixed but can be automatically adjusted based on detected phase relation errors. The system dynamically modifies transmission timing parameters in response to error detection signals, allowing precise synchronization without requiring a large number of fixed delay units.
Data Source
AI summary
A data transceiver system may include an error corrector. The error corrector may include a plurality of delay units, each delay unit being configured to delay a corresponding data signal among a plurality of data signals by a time in response to a corresponding delay code among a plurality of delay codes and outputting the delayed data signal, an error detector configured to receive the plurality of delay codes, determine whether an error has occurred, and output an error signal according to the determination in a data frame lock operation, and a delay controller configured to set initial values of the plurality of delay codes to a predetermined value, vary and output each of the plurality of delay codes in response to a lock signal, and reset initial values the plurality of delay codes in response to the error signal in the data frame lock operation.