Ferroelectric Memory Bit-Cell Design for Low-Energy Storage
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Solution Overview
Problem
Current non-volatile memories, such as NAND or NOR flash, are not suitable for low power and compact computing devices due to high write energy, low density, and high power consumption.
Innovation Solution
The development of high-density low voltage ferroelectric memory bit-cells, which include planar or pillar ferroelectric capacitors, allowing for multi-level programming and higher storage density through vertically stacked capacitors and multi-element gain bit-cells, enabling efficient data sensing and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If non-volatile memories such as NAND or NOR flash are used, then data retention without power is achieved, but write energy consumption is high
Solution Approach 1:
The patent changes the material parameter by using ferroelectric material instead of traditional flash memory materials, enabling non-volatile storage with lower write energy through the ferroelectric effect that allows rapid polarization switching at lower energy costs
Solution Approach 2:
The patent replaces the charge-trapping mechanism of flash memory with a ferroelectric polarization mechanism, substituting the electrical charge storage method with a material property-based storage method that requires less energy for writing while maintaining data retention
2Duration of action of stationary object
If non-volatile memories such as NAND or NOR flash are used, then data retention without power is achieved, but power consumption during operation is high
Solution Approach 1:
The patent changes the operational parameters by utilizing the remnant polarization property of ferroelectric materials, which allows the memory to maintain data states without continuous power supply, significantly reducing operational power consumption compared to volatile memories
Solution Approach 2:
The ferroelectric material provides self-retention of data through its intrinsic remnant polarization, eliminating the need for continuous refresh operations required by DRAM or high-power maintenance circuits, thereby reducing overall power consumption
3Ease of manufacture
If traditional memory structures are used, then manufacturing simplicity is maintained, but storage density is low
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertically stacked capacitor structures, adding the vertical dimension to increase storage density while maintaining compatibility with existing semiconductor manufacturing processes through standard deposition and etching techniques
4Quantity of substance
If vertically stacked capacitors are implemented, then storage density is increased, but device complexity increases
Solution Approach 1:
The patent segments the memory device into modular repeating units of vertically stacked capacitors, where each unit follows the same structural pattern, allowing for scalable fabrication using standardized process modules that reduce overall manufacturing complexity despite the increased density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves higher storage density and reduced power consumption, making it suitable for low power and compact computing devices while maintaining efficient data storage and retrieval.
Implementation Method 1
the capacitor comprises a ferroelectric or paraelectric material
Implementation Method 2
the capacitor comprises a ferroelectric or paraelectric material
Data Source
AI summary
A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.