Semiconductor Memory Device Testing Time Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices require significant time to write test data into all memory cells due to the sequential activation and pre-charging of multiple word lines, which increases the overall testing time.
Innovation Solution
The semiconductor memory device incorporates a command decoder and sensing signal generating circuit that allows for simultaneous activation of multiple word lines and direct data writing into memory cells, reducing the time required for test data writing by maintaining sensing amplifiers active and pre-charging circuits inactive during word line activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential activation and pre-charging of multiple word lines is performed, then reliable data writing into memory cells is achieved, but significant time is consumed for testing
Solution Approach 1:
The sensing amplifiers are activated in advance before the word lines are activated. This preliminary action allows the sensing amplifiers to be ready to immediately latch data when the memory cells are activated, eliminating the need to wait for sequential pre-charging cycles and significantly reducing testing time while maintaining reliable data writing
Solution Approach 2:
The sensing amplifiers remain continuously activated throughout the data writing process across multiple word lines, rather than being deactivated and reactivated for each word line. This continuous operation eliminates idle time between word line activations and maintains the useful action of data latching throughout the entire testing sequence
2Stability of the object's composition
If multiple word lines are activated sequentially with pre-charging, then proper signal levels are maintained, but the number of operation steps increases
Solution Approach 1:
The pre-charging operation is extracted and separated from the main data writing sequence. By removing the pre-charging step that was previously required between word line activations, the number of operation steps is reduced while the sensing amplifier design compensates for maintaining proper signal levels
Solution Approach 2:
The sensing amplifiers are designed to perform multiple functions: they act as both the data latching element and the signal level stabilization mechanism. This multi-functionality eliminates the need for separate pre-charging circuits and operations, reducing overall system complexity while maintaining signal stability
Data Source
AI summary
A semiconductor memory device and a method of testing the same are provided. In the method, the semiconductor memory device enters a test mode after receiving a mode selection signal. After the semiconductor memory device enters the test mode, a first word line is activated. Test data are then sequentially written into a plurality of memory cells coupled to the first word line. The first word line is deactivated, and data between each pair of bit lines are latched. A second word line is activated. After the second word line is activated, the data latched between each pair of bit lines are directly written into the memory cells coupled to the second word line.