Ferroelectric Memory Sub Bit-Line Control
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Solution Overview
Problem
Ferroelectric memories with a bit line hierarchical structure face challenges in reducing bit line parasitic capacitance, leading to increased read voltage requirements and noise propagation, which can result in data disturbance and increased chip area due to the need for additional potential supply lines.
Innovation Solution
A crosspoint ferroelectric memory design that connects sub bit lines to each other and to fixed potentials using n-channel transistors, preventing nonselected sub bit lines from floating and reducing noise propagation, while minimizing the number of required potential supply lines by using only two ground wires for multiple subarrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a bit line hierarchical structure is used to reduce bit line parasitic capacitance, then read voltage is improved, but nonselected sub bit lines enter floating state causing noise propagation and data disturbance
Solution Approach 1:
The memory array is divided into multiple subarrays with separate sub bit lines for each subarray. This segmentation allows independent control of each sub bit line through dedicated transistors connected to potential supply lines, preventing floating states and noise propagation while maintaining reduced parasitic capacitance benefits.
Solution Approach 2:
Transistors are introduced as intermediary components between sub bit lines and potential supply lines. These transistors act as controlled connectors that can be turned on or off to fix the potential of nonselected sub bit lines, preventing noise propagation without permanently increasing parasitic capacitance.
2Reliability
If potential supply lines are added to prevent floating state in nonselected sub bit lines, then data disturbance is reduced, but chip area is increased
Solution Approach 1:
The potential supply lines are designed to serve multiple subarrays simultaneously. By strategically positioning transistors and potential supply lines at shared locations, the same infrastructure can fix potentials for multiple nonselected sub bit lines, reducing the overall number of required potential supply lines and minimizing chip area increase.
3Quantity of substance
If the number of subarrays is increased to improve capacity, then storage capability is improved, but the number of required potential supply lines increases, increasing chip area
Solution Approach 1:
The potential supply line structure is designed with multi-functionality to serve multiple subarrays. Transistors and potential supply lines are positioned at shared locations that can simultaneously fix potentials for nonselected sub bit lines across multiple subarrays, allowing increased storage capacity without proportional increase in chip area.
Solution Approach 2:
Multiple potential supply line functions are merged into a single shared infrastructure. By combining the potential fixing functions for multiple subarrays into unified transistor-controlled connections to common potential supply lines, the patent reduces the total number of separate potential supply lines needed as subarray count increases.
Data Source
AI summary
A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.