Global I/O Line Test Circuit for Semiconductor Memory
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Solution Overview
Problem
The increasing complexity and operating speed of semiconductor memory devices require more data storage and rapid READ/WRITE operations, leading to a proliferation of test modes and global I/O lines, which complicates the internal structure and increases power consumption, making existing testing methods inefficient.
Innovation Solution
An integrated circuit design that incorporates a test circuit using global I/O lines for transmitting test data, a test mode driver, a test mode latch, and a transceiving circuit to manage test mode signals, allowing simultaneous transmission of read/write data and test data through the same lines, reducing the need for additional circuits and simplifying the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test circuits and test mode signal transmission lines are added to enable comprehensive testing of semiconductor memory devices, then testing capability and coverage are improved, but device complexity and chip area increase
Solution Approach 1:
The patent merges the test mode signal transmission function with the existing global I/O lines. The test mode driver transmits test mode signals through the same global I/O lines that carry read/write data, eliminating the need for separate test signal transmission lines. This combining approach maintains comprehensive testing capability while reducing overall device complexity and chip area.
Solution Approach 2:
The global I/O lines are designed to serve multiple functions: they transmit both normal read/write data during operational modes and test mode signals during testing. The test mode driver and latch work together to enable these lines to carry test signals when needed, while the existing transceiving circuits handle both data transmission and test signal reception, achieving multi-functionality without adding dedicated test infrastructure.
2Adaptability or versatility
If multiple test control circuits and latches are added to support various test modes, then test mode coverage is improved, but the number of transmission lines and circuit complexity increase
Solution Approach 1:
The patent combines the transmission of test mode signals with the existing global I/O data lines. Instead of creating separate transmission lines for each test mode signal, the system uses the already-present global I/O lines to carry test mode information when test operations are active. This merging reduces the total number of transmission lines required while maintaining support for multiple test modes.
Solution Approach 2:
The system dynamically switches the function of global I/O lines between data transmission mode and test signal transmission mode. The test mode driver activates test signal transmission only when test operations are required, while the test mode latch holds and transmits the appropriate test mode signal through the global I/O lines. This dynamic allocation allows multiple test modes to be supported without requiring permanent dedicated transmission lines for each mode.
3Productivity
If additional test circuits and dedicated transmission lines are implemented for high-speed testing, then testing speed is improved, but power consumption and circuit complexity increase
Solution Approach 1:
The patent combines test signal transmission with the existing high-speed global I/O data transmission infrastructure. The test mode driver and latch utilize the same high-speed transmission paths that are already optimized for rapid data transfer. By merging test signal transmission into these existing high-speed lines rather than creating separate dedicated test lines, the system maintains high testing speed while avoiding the additional power consumption that would result from duplicating high-speed transmission infrastructure.
Solution Approach 2:
The global I/O lines serve dual purposes: they transmit high-speed read/write data during normal operation and carry test mode signals during testing. The test mode driver and latch enable these universal lines to switch between functions. This multi-functionality allows the system to leverage the already-powerful high-speed transmission capability for testing without adding separate power-hungry test-specific transmission circuits.
Data Source
AI summary
An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.