Semiconductor Memory Bank Control for Coupling Effects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increased integration of semiconductor memory leads to destabilized voltage levels between adjacent word lines due to coupling effects, causing data loss or damage in memory cells, which existing refresh operations like TRR aim to mitigate but may not fully address.
Innovation Solution
A semiconductor memory system that includes a bank control signal generation unit, signal detection unit, and bank enable control unit to manage the active period of memory banks based on detected signals, ensuring stable refresh operations and target row refresh operations, even under PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration degree of semiconductor memory is increased, then memory capacity is improved, but coupling effects between adjacent word lines increase causing voltage destabilization
Solution Approach 1:
The patent performs refresh operations on target word lines before data loss can occur. By detecting when a word line has been activated multiple times and proactively refreshing adjacent word lines, the system prevents voltage destabilization and data loss before they happen, rather than reacting after damage occurs.
Solution Approach 2:
The patent implements a feedback mechanism that counts the number of activations of each word line and uses this information to determine which word lines need refresh operations. The counter detects activation patterns and triggers appropriate refresh operations based on real-time monitoring of word line activity.
2Reliability
If TRR operation is performed to prevent data degradation, then data reliability is improved, but additional operations increase device complexity
Solution Approach 1:
The patent applies refresh operations selectively to specific target word lines rather than performing comprehensive refresh operations on all word lines. By identifying which word lines have been activated multiple times and only refreshing those and their adjacent lines, the system maintains data reliability while reducing unnecessary operations and complexity.
Solution Approach 2:
The patent changes the parameters of refresh operations based on detected activation patterns. Instead of using fixed refresh intervals, the system adjusts refresh timing and targeting based on real-time monitoring of word line activation counts, optimizing the balance between data reliability and operational complexity.
3Productivity
If word line activation frequency is increased to improve access speed, then productivity is improved, but voltage levels become destabilized causing data loss
Solution Approach 1:
The system performs refresh operations on adjacent word lines before voltage destabilization occurs due to high-frequency activations. By detecting activation patterns and proactively refreshing affected word lines, the system maintains data integrity even under high productivity conditions.
Solution Approach 2:
The activation counter provides continuous feedback on word line usage patterns, enabling the system to adjust refresh operations dynamically. This feedback mechanism ensures that data integrity is maintained while allowing high activation frequencies for improved access speed.
Data Source
AI summary
A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for controlling a memory bank based on an active command, a signal detection unit suitable for detecting a firstly activated signal and a lastly activated signal among the bank control signals, and a bank enable control unit suitable for controlling an active period of the memory bank in response to the detected signals.