Asynchronous Dataflow Voltage Control for Low-Power DSP Pipelines
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Solution Overview
Problem
Current embedded computing systems face challenges in achieving high power efficiency due to the breakdown of Dennard's law, leading to increased power consumption per unit area, and existing solutions like multicore processors and voltage scaling have limitations in reducing power density and leakage current.
Innovation Solution
The implementation of asynchronous dataflow architectures with near-threshold voltage (NVT) operating levels and adaptive voltage regulation, which dynamically adjust supply voltage based on workload, reducing power consumption by leveraging asynchronous circuit design and voltage scaling to achieve 10-100× power efficiency improvement over classic CMOS designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Dennard's law scaling is used to increase transistor density, then computing performance is improved, but power density increases
Solution Approach 1:
The patent implements dynamic voltage scaling where the supply voltage to processing elements is adjusted in real-time based on workload demand. When workload decreases, voltage is reduced to minimize dynamic power consumption (P ∝ CV²f). This dynamic adaptation resolves the contradiction by allowing high performance when needed while minimizing power consumption during low-utilization periods, preventing the continuous high power density associated with static high-voltage operation.
Solution Approach 2:
The patent changes the operating voltage parameter of processing elements based on workload conditions. By transitioning between different voltage levels (e.g., from 1.0V to 0.5V), the system can maintain computing performance when required while significantly reducing power consumption when full performance is not needed. This parameter adaptation directly addresses the power-density issue arising from continued transistor scaling.
2Use of energy by moving object
If voltage is reduced to decrease power consumption, then power density is improved, but computing performance deteriorates
Solution Approach 1:
The system dynamically adjusts voltage based on real-time workload detection. When high computing performance is required, voltage is increased to maintain speed. When workload decreases, voltage is reduced to minimize power consumption. This dynamic behavior ensures that performance is maintained when needed while power consumption is optimized during low-utilization periods, resolving the trade-off between power and performance.
Solution Approach 2:
The patent implements feedback mechanisms where the system monitors workload conditions and adjusts voltage accordingly. This closed-loop control ensures that voltage is only reduced when workload permits, maintaining computing performance when high demand is detected while achieving power savings when demand is low. The feedback mechanism prevents performance deterioration by only applying voltage reduction when it is safe to do so.
3Productivity
If clock speed is increased to improve computing performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency scaling where the clock speed of processing elements is adjusted based on workload demand. When high computing performance is required, clock speed is increased to improve productivity. When workload decreases, clock speed is reduced to minimize dynamic power consumption, since dynamic power is proportional to frequency (P ∝ CV²f). This dynamic adjustment resolves the contradiction by matching computational speed to actual demand.
4Productivity
If multicore processors are used to increase chip performance, then productivity is improved, but power density increases
Solution Approach 1:
The patent divides the processing system into multiple independently controllable processing elements that can be selectively activated. Instead of running all cores at full power continuously, the system segments the workload across available elements and deactivates or reduces power to unused elements. This segmentation allows high overall performance when needed while minimizing power density by only activating the necessary number of processing elements for the current workload.
Solution Approach 2:
The system dynamically activates or deactivates processing elements based on workload demand. When high performance is required, more elements are activated. When workload decreases, elements are deactivated or placed in low-power states, reducing overall power consumption. This dynamic resource allocation resolves the contradiction by ensuring that chip performance scales with actual demand rather than maintaining constant high power consumption.
5Use of energy by moving object
If asynchronous dataflow with near-threshold voltage is used, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements self-timed asynchronous circuits where processing elements automatically synchronize their operation based on data availability rather than a global clock. Each element operates independently at near-threshold voltage, activating only when input data is ready and deactivating when idle. This self-service behavior eliminates the need for complex clock distribution networks and timing control logic, achieving high power efficiency without proportionally increasing device complexity. The circuits serve themselves by automatically adapting their operation to workload conditions.
Data Source
AI summary
A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.