Asynchronous Dual-Word-Line SRAM Cell Noise Margin
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Solution Overview
Problem
Conventional memory cells face challenges in maintaining a large noise margin in read and pseudo read modes while operating under ultra-low voltage without increasing power consumption or circuit area, especially due to the impact of reduced source voltage on signal levels and noise margin.
Innovation Solution
A memory cell driven by two word lines in an asynchronous manner, where the second write switch is turned on after the first write switch, preventing noise discharge to unselected cells and allowing operation with a 6 T memory unit, thus enhancing noise margin and area density without additional transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the source voltage is reduced to near-threshold or sub-threshold voltage, then power consumption is reduced, but the signal level and noise margin are reduced making the memory unable to work normally
Solution Approach 1:
The patent divides the conventional single write switch into two separate write switches (first write switch and second write switch) controlled by different word lines. This segmentation allows independent control of noise discharge paths, enabling the memory cell to maintain proper noise margins even when operating at reduced voltages near or below the threshold voltage
Solution Approach 2:
The first write switch is turned on before the second write switch during write operations. This preliminary action of turning on the first write switch establishes a proper discharge path for noise before the second write switch is activated, preventing noise from coupling into unselected cells while maintaining low power operation
2Reliability
If extra transistors are added to separate read and write functions (8T, 10T, 12T memory units), then noise margin in read mode is increased, but circuit area increases by 40% or more
Solution Approach 1:
The patent makes the two write switches serve multiple functions: they separately control noise discharge paths during write operations, enable unselected cell blocking, and work with the latch to maintain data. This multi-functionality allows the 6T cell to achieve noise margins comparable to 8T or 10T designs without adding extra transistors for separate read/write functions
Solution Approach 2:
The patent changes the operational parameters of the existing 6T memory cell by introducing asynchronous control signals with different timing for the two write switches. By adjusting the turn-on timing of each write switch, the patent optimizes noise discharge characteristics and unselected cell blocking without modifying the basic 6T cell structure or adding more transistors
3Reliability
If the number of memory units on the bit line is reduced to increase noise margin, then read noise margin increases, but the circuit area of the memory matrix increases
Solution Approach 1:
The patent extracts the noise discharge function from the bit line by providing dedicated discharge paths through the two write switches. This extraction allows noise to be discharged locally at each memory cell through the write switches rather than requiring reduced bit line capacitance, enabling the memory matrix to maintain high density while achieving adequate noise margins
Data Source
AI summary
A memory comprised of a plurality of single port SRAM memory cells, each driven by two word lines in an asynchronous manner has a hold mode, a read mode and a write mode. Each of the single port SRAM memory cells includes a first write switch, a second write switch and a latch. The first write switch is electrically connected to a first word line and is turned on by a first turn-on signal transmitted by the first word line. The second write switch is electrically connected to a second word line and is turned on by a second turn-on signal transmitted by the second word line. When the memory is in the write mode, the second write switch is turned on by the second turn-on signal having a delay with respect to the first turn-on signal, thereby blocking the pseudo read of the unselected memory cell.