Asynchronous Fork Circuit Blocking Premature Switching Delays

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Solution Overview

Problem

Asynchronous circuits with isochronous forks are prone to malfunctions due to variations in propagation delays between branches, which can exceed the slack, leading to premature switching and operational failures.

Innovation Solution

Incorporating a blocking circuit with a Muller gate at each logic gate to prevent signal propagation when end-of-branch signals are in different logic states, and using bypass circuits to ensure all terminals are considered, thereby preventing premature switching and ensuring operation regardless of delay variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If an isochronous fork is used in an asynchronous circuit, then the circuit can perform logic functions with single-output logic elements, but the circuit becomes sensitive to propagation delay variations between branches

Engineering Contradiction:
Improvelogic function capabilityVSAvoidoperation reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The blocking circuit proactively prevents signal propagation before a hazard can occur. By detecting unequal branch states in advance and blocking the output signal, the circuit avoids premature switching and maintains reliable operation despite delay variations in isochronous forks

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The blocking circuit acts as an intermediary between the isochronous fork and the rest of the circuit. It monitors the state of all branches and only allows signal propagation when all branches are in the same state, thereby mediating the conflict between delay variations and reliable operation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If the slack in an asynchronous circuit is exceeded, then the circuit can handle larger delay variations, but premature switching occurs leading to operational failures

Engineering Contradiction:
Improvetemporal marginVSAvoidfunctional correctness
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The blocking circuit performs preliminary checking of branch states before allowing signal propagation. This prevents premature switching by ensuring all branches are in the same state, thereby maintaining functional correctness even when the slack is exceeded

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The blocking circuit provides a protective mechanism that cushions against the harmful effects of excessive delay variations. By blocking signals when branch states differ, it prevents operational failures that would otherwise occur when slack is exceeded

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentEP2637310B1Asynchronous circuit that is not sensitive to delays
Publication Date: 2015.01.21 TIEMPO
  • EP2637310B1 patent drawingFigure 1~3
  • EP2637310B1 patent drawingFigure 4~6
  • EP2637310B1 patent drawingFigure 7~8

AI summary

The asynchronous circuit comprises a fork (F) with at least two branches (B0, B1), each branch being connected to a logic gate (G0, G1) so that the logic gate receives as input an end of branch signal (X0 , X1). It further comprises a branch end signal branch circuit (2a, 2b) at each logic gate to form a derived signal (X0', X1'), and a blocking circuit comprising a Muller gate (C ) and receiving at least one derivative signal as input, the blocking circuit being configured to prevent the propagation of an output signal (Eack) when the end of branch signals (X0, X1) are in different logic states.