Asynchronous FSM Arc Cell for Glitch-Suppressed State Transitions
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Solution Overview
Problem
Asynchronous finite state machine (FSM) circuits face issues with glitches causing unpredictable transitions and potential deadlocks due to aperiodic transient signals, leading to increased power consumption and latency in conventional solutions.
Innovation Solution
The implementation of an arc cell in the FSM circuit that includes a feedback mechanism to ensure stable transitions by suppressing or latching glitches, preventing their propagation and ensuring known states, using a MOSFET-based inverter and logic gates to condition signal propagation based on glitch detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional solutions (Min_TON/Min_TOFF analog circuitry, glitch-free comparators, or redundant asynchronous design) are used to address glitch issues, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent introduces a latch circuit as an intermediary element between the asynchronous FSM and the output. This latch captures the state information and provides a stable output signal, mediating between the potentially glitch-prone asynchronous logic and the output requirements, thereby eliminating glitches without requiring complex redundant design throughout the entire system
Solution Approach 2:
The patent extracts the glitch-prone asynchronous logic from the critical path by using a separate latch circuit to capture and stabilize the output. The asynchronous FSM operates independently, and only its finalized state is transferred to the latch, separating the glitch generation source from the output path and simplifying the overall design
2Reliability
If conventional solutions (Min_TON/Min_TOFF analog circuitry, glitch-free comparators, or redundant asynchronous design) are used to address glitch issues, then reliability is improved, but power consumption increases
Solution Approach 1:
The latch circuit acts as an energy-efficient intermediary that captures state information only when transitions occur, rather than continuously operating complex redundant circuits. The latch holds the captured value stable, providing glitch-free output without requiring continuous power consumption of elaborate glitch-detection and correction circuitry throughout the system
Solution Approach 2:
The asynchronous FSM inherently provides its own state information through the request/acknowledge mechanism, and the latch automatically captures this information when stable. The system serves itself by using its own operational characteristics to drive the latch, eliminating the need for additional power-hungry control circuits that would be required in conventional synchronous designs
3Reliability
If conventional solutions (Min_TON/Min_TOFF analog circuitry, glitch-free comparators, or redundant asynchronous design) are used to address glitch issues, then reliability is improved, but latency increases
Solution Approach 1:
The latch circuit introduces minimal delay only at the output stage, rather than requiring continuous synchronization and validation delays throughout the entire asynchronous FSM. The latch quickly captures the stable state value and provides it as output, adding negligible latency while ensuring glitch-free operation at the critical output interface
Data Source
AI summary
An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.