Asynchronous Memory Scheduler Using Predicted Timing
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Solution Overview
Problem
Conventional memory access scheduling techniques are ineffective for multi-core processors and multi-threaded applications due to interleaving of memory access requests to disparate locations, leading to reduced throughput and increased latency.
Innovation Solution
An asynchronous memory scheduling technique that uses memory timing and state information, along with a scheduler operating at a different clock frequency than the memory access controller, to select and reorder memory access requests, thereby optimizing memory access sequences and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory access scheduling techniques are used, then memory access is simplified, but throughput decreases and latency increases due to ineffective handling of interleaved requests from multiple cores
Solution Approach 1:
The patent implements a dynamic scheduling system that adapts to changing memory access patterns from multiple processor cores. The scheduler continuously monitors pending requests and dynamically reorders them based on predicted memory timing and state information, transforming a static scheduling approach into a dynamic one that can handle interleaved requests effectively.
Solution Approach 2:
The system performs preliminary actions by predicting future memory timing and state information before actual memory access occurs. The scheduler uses predicted activate times, precharge times, and memory bank states to pre-order requests in an optimal sequence, allowing the memory controller to execute accesses more efficiently without waiting for real-time feedback.
2Productivity
If memory access requests are reordered to optimize throughput, then latency may increase due to reordering operations, but overall efficiency improves
Solution Approach 1:
The scheduling system incorporates feedback mechanisms by continuously monitoring the actual memory timing and state information compared to predicted values. This feedback allows the scheduler to adjust its predictions and reordering decisions, ensuring that latency is minimized while maintaining high throughput through iterative optimization.
Solution Approach 2:
The system changes scheduling parameters dynamically based on predicted memory timing and state information. By adjusting the reorder sequence according to predicted activate times, precharge times, and bank availability, the system optimizes both throughput and latency by finding the best parameter configuration for current memory conditions.
3Productivity
If a synchronous scheduling approach is used, then clock synchronization is simplified, but the scheduler cannot consider enough pending requests to optimize performance
Solution Approach 1:
The patent introduces an intermediary translation layer between the asynchronous scheduler and the synchronous memory controller. This intermediary component translates the asynchronous scheduling decisions into synchronous memory access commands, allowing the scheduler to consider more pending requests without creating complex timing issues in the memory interface.
Data Source
AI summary
A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time.